Xuan Zeng
Orcid: 0000-0002-8097-4053Affiliations:
- Fudan University, State Key Lab of ASIC & System, School of Microelectronics, Shanghai, China
According to our database1,
Xuan Zeng
authored at least 241 papers
between 1999 and 2024.
Collaborative distances:
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Bibliography
2024
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., April, 2024
BBGP-sDFO: Batch Bayesian and Gaussian Process Enhanced Subspace Derivative Free Optimization for High-Dimensional Analog Circuit Synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., February, 2024
pNeurFill: Enhanced Neural Network Model-Based Dummy Filling Synthesis With Perimeter Adjustment.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., February, 2024
Yield Optimization for Analog Circuits over Multiple Corners via Bayesian Neural Networks: Enhancing Circuit Reliability under Environmental Variation.
ACM Trans. Design Autom. Electr. Syst., January, 2024
2023
High-Level Topology Synthesis Method for Δ-Σ Modulators via Bi-Level Bayesian Optimization.
IEEE Trans. Circuits Syst. II Express Briefs, December, 2023
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2023
Unleashing the Power of Graph Spectral Sparsification for Power Grid Analysis via Incomplete Cholesky Factorization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., September, 2023
ACM Trans. Design Autom. Electr. Syst., March, 2023
A path integral Monte Carlo (PIMC) method based on Feynman-Kac formula for electrical impedance tomography.
J. Comput. Phys., March, 2023
A Batched Bayesian Optimization Approach for Analog Circuit Synthesis via Multi-Fidelity Modeling.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., February, 2023
Correlated Bayesian Model Fusion: Efficient High-Dimensional Performance Modeling of Analog/RF Integrated Circuits Over Multiple Corners.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., February, 2023
ESPSim: An Efficient Scalable Power Grid Simulator Based on Parallel Algebraic Multigrid.
ACM Trans. Design Autom. Electr. Syst., January, 2023
IEEE Trans. Circuits Syst. I Regul. Pap., 2023
Proceedings of the 24th International Symposium on Quality Electronic Design, 2023
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023
Automated and Agile Design of Layout Hotspot Detector via Neural Architecture Search.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
cVTS: A Constrained Voronoi Tree Search Method for High Dimensional Analog Circuit Synthesis.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
2022
A Parallel Iterative Probabilistic Method for Mixed Problems of Laplace Equations with the Feynman-Kac Formula of Killed Brownian Motions.
SIAM J. Sci. Comput., October, 2022
ACM Trans. Design Autom. Electr. Syst., 2022
Learning From Highly Confident Samples for Automatic Knee Osteoarthritis Severity Assessment: Data From the Osteoarthritis Initiative.
IEEE J. Biomed. Health Informatics, 2022
An Efficient Batch-Constrained Bayesian Optimization Approach for Analog Circuit Synthesis via Multiobjective Acquisition Ensemble.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
Fast Statistical Analysis of Rare Failure Events With Truncated Normal Distribution in High-Dimensional Variation Space.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
LinEasyBO: Scalable Bayesian Optimization Approach for Analog Circuit Synthesis via One-Dimensional Subspaces.
Proceedings of the 2022 ACM/IEEE Workshop on Machine Learning for CAD, 2022
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
SAT-based Scheduling Algorithm for High-level Synthesis Considering Resource Sharing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
A Batch Bayesian Optimization Approach For Analog Circuit Synthesis Based On Multi-Points Selection Criterion.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
A High-Precision Stochastic Solver for Steady-State Thermal Analysis with Fourier Heat Transfer Robin Boundary Conditions.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
Topology Optimization of Operational Amplifier in Continuous Space via Graph Embedding.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
An efficient yield optimization method for analog circuits via gaussian process classification and varying-sigma sampling.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022
A Novel and Efficient Bayesian Optimization Approach for Analog Designs with Multi-Testbench.
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022
2021
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
A Novel and Unified Full-Chip CMP Model Aware Dummy Fill Insertion Framework With SQP-Based Optimization Method.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
An Efficient Batch Constrained Bayesian Optimization Approach for Analog Circuit Synthesis via Multi-objective Acquisition Ensemble.
CoRR, 2021
Bayesian Optimization Approach for Analog Circuit Design Using Multi-Task Gaussian Process.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021
Accelerate Logic Re-simulation on GPU via Gate/Event Parallelism and State Compression.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021
When Wafer Failure Pattern Classification Meets Few-shot Learning and Self-Supervised Learning.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021
An Efficient Yield Estimation Method for Layouts of High Dimensional and High Sigma SRAM Arrays.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
Automated Compensation Scheme Design for Operational Amplifier via Bayesian Optimization.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021
NeurFill: Migrating Full-Chip CMP Simulators to Neural Networks for Model-Based Dummy Filling Synthesis.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021
A Robust Batch Bayesian Optimization for Analog Circuit Synthesis via Local Penalization.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021
Bayesian Inference on Introduced General Region: An Efficient Parametric Yield Estimation Method for Integrated Circuits.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021
High-Dimensional Bayesian Optimization for Automated Analog Circuit Design via Add-Graph Structure.
Proceedings of the 14th IEEE International Conference on ASIC, 2021
Efficient High-Level Synthesis of Approximate Computing Circuits via Multi-fidelity Modeling.
Proceedings of the 14th IEEE International Conference on ASIC, 2021
A Fast Aging-aware Static Timing Analysis Prediction Frame of Digital Integrated Circuits.
Proceedings of the 14th IEEE International Conference on ASIC, 2021
2020
ACM Trans. Design Autom. Electr. Syst., 2020
Improved Low-Power Cost-Effective DCT Implementation Based on Markov Random Field and Stochastic Logic.
IEEE Trans. Circuits Syst. Video Technol., 2020
Efficient Statistical Analysis for Correlated Rare Failure Events via Asymptotic Probability Approximation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
Efficient Parametric Yield Estimation Over Multiple Process Corners via Bayesian Inference Based on Bernoulli Distribution.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
Efficient Rare Failure Analysis Over Multiple Corners via Correlated Bayesian Inference.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
Neural Comput. Appl., 2020
CoRR, 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Multi-Corner Parametric Yield Estimation via Bayesian Inference on Bernoulli Distribution with Conjugate Prior.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020
An Efficient Bayesian Optimization Approach for Analog Circuit Synthesis via Sparse Gaussian Process Modeling.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
An Efficient Asynchronous Batch Bayesian Optimization Approach for Analog Circuit Synthesis.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
An Efficient and Robust Yield Optimization Method for High-dimensional SRAM Circuits.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020
2019
Radiation-Hardened 14T SRAM Bitcell With Speed and Power Optimized for Space Application.
IEEE Trans. Very Large Scale Integr. Syst., 2019
An Efficient FPGA Implementation of Orthogonal Matching Pursuit With Square-Root-Free QR Decomposition.
IEEE Trans. Very Large Scale Integr. Syst., 2019
An Efficient Memory Partitioning Approach for Multi-Pattern Data Access via Data Reuse.
ACM Trans. Reconfigurable Technol. Syst., 2019
Graph-Constrained Sparse Performance Modeling for Analog Circuit Optimization via SDP Relaxation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019
An inverter chain with parallel output nodes for eliminating single-event transient pulse.
IEICE Electron. Express, 2019
IEICE Electron. Express, 2019
Efficient Performance Trade-off Modeling for Analog Circuit based on Bayesian Neural Network.
Proceedings of the International Conference on Computer-Aided Design, 2019
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
An Efficient FPGA-based Floating Random Walk Solver for Capacitance Extraction using SDAccel.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
An Efficient Multi-fidelity Bayesian Optimization Approach for Analog Circuit Synthesis.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
Proceedings of the 13th IEEE International Conference on ASIC, 2019
Proceedings of the 13th IEEE International Conference on ASIC, 2019
Proceedings of the 13th IEEE International Conference on ASIC, 2019
2018
Thermal Stress and Reliability Analysis of TSV-Based 3-D ICs With a Novel Adaptive Strategy Finite Element Method.
IEEE Trans. Very Large Scale Integr. Syst., 2018
Cut Redistribution and Insertion for Advanced 1-D Layout Design via Network Flow Optimization.
IEEE Trans. Very Large Scale Integr. Syst., 2018
IEEE Trans. Very Large Scale Integr. Syst., 2018
ACM Trans. Design Autom. Electr. Syst., 2018
An Efficient Bayesian Optimization Approach for Automated Optimization of Analog Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
Interlayer Cooling Network Design for High-Performance 3D ICs Using Channel Patterning and Pruning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
Smart-MSP: A Self-Adaptive Multiple Starting Point Optimization Approach for Analog Circuit Synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
Efficient Yield Optimization for Analog and SRAM Circuits via Gaussian Process Regression and Adaptive Yield Estimation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
Low-Power Noise-Immune Nanoscale Circuit Design Using Coding-Based Partial MRF Method.
IEEE J. Solid State Circuits, 2018
Offset voltage suppressed sense amplifier with self-adaptive distribution transformation technique.
IEICE Electron. Express, 2018
A dual-output hardening design of inverter chain for P-hit single-event transient pulse elimination.
IEICE Electron. Express, 2018
A novel single-arm-worn 24 h heart disease monitor empowered by machine intelligence.
Biomed. Signal Process. Control., 2018
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018
Batch Bayesian Optimization via Multi-objective Acquisition Ensemble for Automated Analog Circuit Design.
Proceedings of the 35th International Conference on Machine Learning, 2018
Proceedings of the International Conference on Computer-Aided Design, 2018
A general graph based pessimism reduction framework for design optimization of timing closure.
Proceedings of the 55th Annual Design Automation Conference, 2018
Proceedings of the 55th Annual Design Automation Conference, 2018
2017
High-Dimensional and Multiple-Failure-Region Importance Sampling for SRAM Yield Analysis.
IEEE Trans. Very Large Scale Integr. Syst., 2017
An Effective Layout Decomposition Method for DSA with Multiple Patterning in Contact-Hole Generation.
ACM Trans. Design Autom. Electr. Syst., 2017
Optimization and Quality Estimation of Circuit Design via Random Region Covering Method.
ACM Trans. Design Autom. Electr. Syst., 2017
C-YES: An Efficient Parametric Yield Estimation Approach for Analog and Mixed-Signal Circuits Based on Multicorner-Multiperformance Correlations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017
Improved Tangent Space-Based Distance Metric for Lithographic Hotspot Classification.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017
A Novel Framework for Motion-Tolerant Instantaneous Heart Rate Estimation by Phase-Domain Multiview Dynamic Time Warping.
IEEE Trans. Biomed. Eng., 2017
An efficient and robust method to determine the optimal tap coefficients of high speed FIR equalizer.
Sci. China Inf. Sci., 2017
HeartID: A Multiresolution Convolutional Neural Network for ECG-Based Biometric Human Identification in Smart Health Applications.
IEEE Access, 2017
A Machine Learning-Empowered System for Long-Term Motion-Tolerant Wearable Monitoring of Blood Pressure and Heart Rate With Ear-ECG/PPG.
IEEE Access, 2017
Proceedings of the 2017 IFIP/IEEE International Conference on Very Large Scale Integration, 2017
Proceedings of the 8th IEEE Annual Ubiquitous Computing, 2017
Proceedings of the 8th IEEE Annual Ubiquitous Computing, 2017
Proceedings of the 2017 IEEE International Symposium on Parallel and Distributed Processing with Applications and 2017 IEEE International Conference on Ubiquitous Computing and Communications (ISPA/IUCC), 2017
Efficient spectral graph sparsification via Krylov-subspace based spectral perturbation analysis.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017
An efficient leakage-aware thermal simulation approach for 3D-ICs using corrected linearized model and algebraic multigrid.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
Subgradient based multiple-starting-point algorithm for non-smooth optimization of analog circuits.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
Proceedings of the 54th Annual Design Automation Conference, 2017
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017
Proceedings of the 12th IEEE International Conference on ASIC, 2017
2016
Layout Decomposition Co-Optimization for Hybrid E-Beam and Multiple Patterning Lithography.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016
Harvesting Design Knowledge From the Internet: High-Dimensional Performance Tradeoff Modeling for Large-Scale Analog Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016
Efficient Spatial Variation Modeling of Nanoscale Integrated Circuits Via Hidden Markov Tree.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016
Efficient Hybrid Performance Modeling for Analog Circuits Using Hierarchical Shrinkage Priors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016
A yield-enhanced global optimization methodology for analog circuit based on extreme value theory.
Sci. China Inf. Sci., 2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Fast compressive sensing reconstruction algorithm on FPGA using Orthogonal Matching Pursuit.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Efficient statistical analysis for correlated rare failure events via asymptotic probability approximation.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016
Proceedings of the 35th International Conference on Computer-Aided Design, 2016
Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016
Efficient multiple starting point optimization for automated analog circuit optimization via recycling simulation data.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
Efficient performance modeling via Dual-Prior Bayesian Model Fusion for analog and mixed-signal circuits.
Proceedings of the 53rd Annual Design Automation Conference, 2016
Efficient performance modeling of analog integrated circuits via kernel density based sparse regression.
Proceedings of the 53rd Annual Design Automation Conference, 2016
Algorithms in ParAFEMImp: A Parallel and Wideband Impedance Extraction Program for Complicated 3-D Geometries.
Proceedings of the 2nd IEEE International Conference on Big Data Security on Cloud, 2016
An efficient trajectory-based algorithm for model order reduction of nonlinear systems via localized projection and global interpolation.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016
2015
Automated Technology Migration Methodology for Mixed-Signal Circuit Based on Multistart Optimization Framework.
IEEE Trans. Very Large Scale Integr. Syst., 2015
Layout Decomposition with Pairwise Coloring and Adaptive Multi-Start for Triple Patterning Lithography.
ACM Trans. Design Autom. Electr. Syst., 2015
Efficient Transient Analysis of Power Delivery Network With Clock/Power Gating by Sparse Approximation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015
MOS Table Models for Fast and Accurate Simulation of Analog and Mixed-Signal Circuits Using Efficient Oscillation-Diminishing Interpolations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015
Rapid estimation of the probability of SRAM failure via adaptive multi-level sliding-window statistical method.
Integr., 2015
Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Efficient multivariate moment estimation via Bayesian model fusion for analog and mixed-signal circuits.
Proceedings of the 52nd Annual Design Automation Conference, 2015
Proceedings of the 14th International Conference on Computer-Aided Design and Computer Graphics, 2015
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015
Layout decomposition co-optimization for hybrid e-beam and multiple patterning lithography.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015
2014
IEEE Trans. Very Large Scale Integr. Syst., 2014
Efficient Statistical Timing Analysis for Circuits with Post-Silicon Tunable Buffers.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
BMF-BD: Bayesian Model Fusion on Bernoulli Distribution for Efficient Yield Estimation of Integrated Circuits.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014
2013
Near-Field Communication Transceiver System Modeling and Analysis Using SystemC/SystemC-AMS With the Consideration of Noise Issues.
IEEE Trans. Very Large Scale Integr. Syst., 2013
IEEE Trans. Circuits Syst. I Regul. Pap., 2013
A Parallel Method for Solving Laplace Equations with Dirichlet Data Using Local Boundary Integral Equations and Random Walks.
SIAM J. Sci. Comput., 2013
Post-routing layer assignment for double patterning with timing critical paths consideration.
Integr., 2013
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013
A parallel sparse linear system solver for large-scale circuit simulation based on Schur Complement.
Proceedings of the IEEE 10th International Conference on ASIC, 2013
Proceedings of the IEEE 10th International Conference on ASIC, 2013
FMSSQP: An efficient global optimization tool for the robust design of Rail-to-Rail Op-Amp.
Proceedings of the IEEE 10th International Conference on ASIC, 2013
Proceedings of the IEEE 10th International Conference on ASIC, 2013
Proceedings of the IEEE 10th International Conference on ASIC, 2013
Mixed-signal system verification by SystemC/SystemC-AMS and HSIM-VCS in near field communication tag design.
Proceedings of the IEEE 10th International Conference on ASIC, 2013
2012
Yield-Driven Clock Skew Scheduling for Arbitrary Distributions of Critical Path Delays.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012
AMOR: an efficient aggregating based model order reduction method for many-terminal interconnect circuits.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012
Improved tangent space based distance metric for accurate lithographic hotspot classification.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012
2011
Full-Spectrum Spatial-Temporal Dynamic Thermal Analysis for Nanometer-Scale Integrated Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2011
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011
Stochastic Non-homogeneous Arnoldi Method for Analysis of On-Chip Power Grid Networks under Process Variations.
IEICE Trans. Electron., 2011
A new method for multiparameter robust stability distribution analysis of linear analog circuits.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011
Proceedings of the Design, Automation and Test in Europe, 2011
Proceedings of the 48th Design Automation Conference, 2011
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011
2010
A Wavelet-Collocation-Based Trajectory Piecewise-Linear Algorithm for Time-Domain Model-Order Reduction of Nonlinear Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010
NHAR: A non-homogeneous Arnoldi method for fast simulation of RCL circuits with a large number of ports.
Int. J. Circuit Theory Appl., 2010
Stochastic Sparse-Grid Collocation Algorithm for Steady-State Analysis of Nonlinear System with Process Variations.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010
Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures, 2010
An efficient transistor-level piecewise-linear macromodeling approach for model order reduction of nonlinear circuits.
Proceedings of the Design, Automation and Test in Europe, 2010
Proceedings of the 47th Design Automation Conference, 2010
2009
Generalized Stochastic Collocation Method for Variation-Aware Capacitance Extraction of Interconnects Considering Arbitrary Random Probability.
IEICE Trans. Electron., 2009
A Modified Nested Sparse Grid Based Adaptive Stochastic Collocation Method for Statistical Static Timing Analysis.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009
Intra-Die Spatial Correlation Extraction with Maximum Likelihood Estimation Method for Multiple Test Chips.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009
Proceedings of the 46th Design Automation Conference, 2009
Proceedings of the 46th Design Automation Conference, 2009
Proceedings of the 46th Design Automation Conference, 2009
Statistical analysis of on-chip power grid networks by variational extended truncated balanced realization method.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009
2008
Model Order Reduction of Parameterized Interconnect Networks via a Two-Directional Arnoldi Process.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008
Adaptive Stochastic Collocation Method for Parameterized Statistical Timing Analysis with Quadratic Delay Model.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008
Adaptive Stochastic Collocation Method (ASCM) for Parameterized Statistical Timing Analysis with Quadratic Delay Model.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008
Timing yield driven clock skew scheduling considering non-Gaussian distributions of critical path delays.
Proceedings of the 45th Design Automation Conference, 2008
2007
A Novel Optimization Method for Parametric Yield: Uniform Design Mapping Distance Algorithm.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007
RLCSYN: RLC Equivalent Circuit Synthesis for Structure-Preserved Reduced-order Model of Interconnect.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007
A sparse grid based spectral stochastic collocation method for variations-aware capacitance extraction of interconnects under nanometer process technology.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007
WCOMP: Waveform Comparison Tool for Mixed-signal Validation Regression in Memory Design.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007
Stochastic Sparse-grid Collocation Algorithm (SSCA) for Periodic Steady-State Analysis of Nonlinear System with Process Variations.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007
2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
A Spectral Stochastic Collocation Method for Capacitance Extraction of Interconnects with Process Variations.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006
2005
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005
Power-optimal simultaneous buffer insertion/sizing and uniform wire sizing for single long wires.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005
Block SAPOR: block Second-order Arnoldi method for Passive Order Reduction of multi-input multi-output RCS interconnect circuits.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005
2004
Frequency domain wavelet method with GMRES for large-scale linear circuit simulation.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
Two-sided projection method in variational equation model order reduction of nonlinear circuits.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004
Steady-State Analysis of Nonlinear Circuits Using Discrete Singular Convolution Method.
Proceedings of the 2004 Design, 2004
Proceedings of the 2004 Design, 2004
Analog circuit behavioral modeling via wavelet collocation method with auto-companding.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004
2003
Behavioral modeling for analog system-level simulation by wavelet collocation method.
IEEE Trans. Circuits Syst. II Express Briefs, 2003
An error distribution based nonlinear companding method for analog behavioral modeling via wavelet approximation.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
An efficient Sylvester equation solver for time domain circuit simulation by wavelet collocation method.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003
2002
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002
2001
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001
2000
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
1999
Proceedings of the 1999 International Symposium on Physical Design, 1999
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999