Dian Zhou

According to our database1, Dian Zhou authored at least 151 papers between 1989 and 2020.

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Bibliography

2020
Analog/RF Post-silicon Tuning via Bayesian Optimization.
ACM Trans. Design Autom. Electr. Syst., 2020

Efficient Statistical Analysis for Correlated Rare Failure Events via Asymptotic Probability Approximation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Efficient Parametric Yield Estimation Over Multiple Process Corners via Bayesian Inference Based on Bernoulli Distribution.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Efficient Rare Failure Analysis Over Multiple Corners via Correlated Bayesian Inference.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Nonlinear CNN: improving CNNs with quadratic convolutions.
Neural Comput. Appl., 2020

Projection based Active Gaussian Process Regression for Pareto Front Modeling.
CoRR, 2020

Application of Deep Learning Algorithm in Feature Mining and Rapid Identification of Colorectal Image.
IEEE Access, 2020

An Efficient Bayesian Optimization Approach for Analog Circuit Synthesis via Sparse Gaussian Process Modeling.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

An Efficient Asynchronous Batch Bayesian Optimization Approach for Analog Circuit Synthesis.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

An Efficient and Robust Yield Optimization Method for High-dimensional SRAM Circuits.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

Bayesian Methods for the Yield Optimization of Analog and SRAM Circuits.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

2019
An Efficient FPGA Implementation of Orthogonal Matching Pursuit With Square-Root-Free QR Decomposition.
IEEE Trans. Very Large Scale Integr. Syst., 2019

An Efficient Memory Partitioning Approach for Multi-Pattern Data Access via Data Reuse.
ACM Trans. Reconfigurable Technol. Syst., 2019

Graph-Constrained Sparse Performance Modeling for Analog Circuit Optimization via SDP Relaxation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Vulnerability Detection in Firmware Based on Clonal Selection Algorithm.
Proceedings of the IEEE Symposium Series on Computational Intelligence, 2019

Efficient Performance Trade-off Modeling for Analog Circuit based on Bayesian Neural Network.
Proceedings of the International Conference on Computer-Aided Design, 2019

VSkLCG A Method for Cross-Platform Vulnerability Search in Firmware.
Proceedings of the 6th International Conference on Dependable Systems and Their Applications, 2019

Bayesian Optimization Approach for Analog Circuit Synthesis Using Neural Network.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

An Efficient FPGA-based Floating Random Walk Solver for Capacitance Extraction using SDAccel.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

An Efficient Multi-fidelity Bayesian Optimization Approach for Analog Circuit Synthesis.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Efficient Layout Hotspot Detection via Binarized Residual Neural Network.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Learning Sparse Patterns in Deep Neural Networks.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

Parallel Global Placement on CPU via Parallel Reduction.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

2018
Thermal Stress and Reliability Analysis of TSV-Based 3-D ICs With a Novel Adaptive Strategy Finite Element Method.
IEEE Trans. Very Large Scale Integr. Syst., 2018

Cut Redistribution and Insertion for Advanced 1-D Layout Design via Network Flow Optimization.
IEEE Trans. Very Large Scale Integr. Syst., 2018

An Efficient Non-Gaussian Sampling Method for High Sigma SRAM Yield Analysis.
ACM Trans. Design Autom. Electr. Syst., 2018

An Efficient Bayesian Optimization Approach for Automated Optimization of Analog Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

Interlayer Cooling Network Design for High-Performance 3D ICs Using Channel Patterning and Pruning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Smart-MSP: A Self-Adaptive Multiple Starting Point Optimization Approach for Analog Circuit Synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Efficient Yield Optimization for Analog and SRAM Circuits via Gaussian Process Regression and Adaptive Yield Estimation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

A novel single-arm-worn 24 h heart disease monitor empowered by machine intelligence.
Biomed. Signal Process. Control., 2018

Batch Bayesian Optimization via Multi-objective Acquisition Ensemble for Automated Analog Circuit Design.
Proceedings of the 35th International Conference on Machine Learning, 2018

An efficient data reuse strategy for multi-pattern data access.
Proceedings of the International Conference on Computer-Aided Design, 2018

An efficient Bayesian yield estimation method for high dimensional and high sigma SRAM circuits.
Proceedings of the 55th Annual Design Automation Conference, 2018

A general graph based pessimism reduction framework for design optimization of timing closure.
Proceedings of the 55th Annual Design Automation Conference, 2018

Multi-objective bayesian optimization for analog/RF circuit synthesis.
Proceedings of the 55th Annual Design Automation Conference, 2018

2017
High-Dimensional and Multiple-Failure-Region Importance Sampling for SRAM Yield Analysis.
IEEE Trans. Very Large Scale Integr. Syst., 2017

An Effective Layout Decomposition Method for DSA with Multiple Patterning in Contact-Hole Generation.
ACM Trans. Design Autom. Electr. Syst., 2017

Optimization and Quality Estimation of Circuit Design via Random Region Covering Method.
ACM Trans. Design Autom. Electr. Syst., 2017

C-YES: An Efficient Parametric Yield Estimation Approach for Analog and Mixed-Signal Circuits Based on Multicorner-Multiperformance Correlations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Improved Tangent Space-Based Distance Metric for Lithographic Hotspot Classification.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Efficient Memory Partitioning for Parallel Data Access in FPGA via Data Reuse.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

A Novel Framework for Motion-Tolerant Instantaneous Heart Rate Estimation by Phase-Domain Multiview Dynamic Time Warping.
IEEE Trans. Biomed. Eng., 2017

An efficient and robust method to determine the optimal tap coefficients of high speed FIR equalizer.
Sci. China Inf. Sci., 2017

HeartID: A Multiresolution Convolutional Neural Network for ECG-Based Biometric Human Identification in Smart Health Applications.
IEEE Access, 2017

A Machine Learning-Empowered System for Long-Term Motion-Tolerant Wearable Monitoring of Blood Pressure and Heart Rate With Ear-ECG/PPG.
IEEE Access, 2017

PulsePrint: Single-arm-ECG biometric human identification using deep learning.
Proceedings of the 8th IEEE Annual Ubiquitous Computing, 2017

Hear the heart: Daily cardiac health monitoring using Ear-ECG and machine learning.
Proceedings of the 8th IEEE Annual Ubiquitous Computing, 2017

Study on mechanical properties of radial permanent magnet bearing.
Proceedings of the 2017 IEEE International Conference on Cybernetics and Intelligent Systems (CIS) and IEEE Conference on Robotics, 2017

A Novel N-Retry Transactional Memory Model for Multi-Thread Programming.
Proceedings of the 2017 IEEE International Symposium on Parallel and Distributed Processing with Applications and 2017 IEEE International Conference on Ubiquitous Computing and Communications (ISPA/IUCC), 2017

Efficient spectral graph sparsification via Krylov-subspace based spectral perturbation analysis.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

A grid-based detailed routing algorithm for advanced 1D process.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Efficient SVM-based hotspot detection using spectral clustering.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

An efficient leakage-aware thermal simulation approach for 3D-ICs using corrected linearized model and algebraic multigrid.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Subgradient based multiple-starting-point algorithm for non-smooth optimization of analog circuits.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Correlated Rare Failure Analysis via Asymptotic Probability Evaluation.
Proceedings of the 54th Annual Design Automation Conference, 2017

Network flow based cut redistribution and insertion for advanced 1D layout design.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

An efficient algorithm for stencil planning and optimization in E-beam lithography.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016
Layout Decomposition Co-Optimization for Hybrid E-Beam and Multiple Patterning Lithography.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Efficient Spatial Variation Modeling of Nanoscale Integrated Circuits Via Hidden Markov Tree.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Efficient Hybrid Performance Modeling for Analog Circuits Using Hierarchical Shrinkage Priors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

A yield-enhanced global optimization methodology for analog circuit based on extreme value theory.
Sci. China Inf. Sci., 2016

PATer: A Hardware Prefetching Automatic Tuner on IBM POWER8 Processor.
IEEE Comput. Archit. Lett., 2016

High-speed link verification based on statistical inference.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Fast compressive sensing reconstruction algorithm on FPGA using Orthogonal Matching Pursuit.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Efficient statistical analysis for correlated rare failure events via asymptotic probability approximation.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Efficient Memory Partitioning for Parallel Data Access via Data Reuse.
Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016

Efficient multiple starting point optimization for automated analog circuit optimization via recycling simulation data.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Efficient spatial variation modeling via robust dictionary learning.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Efficient performance modeling via Dual-Prior Bayesian Model Fusion for analog and mixed-signal circuits.
Proceedings of the 53rd Annual Design Automation Conference, 2016

Efficient performance modeling of analog integrated circuits via kernel density based sparse regression.
Proceedings of the 53rd Annual Design Automation Conference, 2016

An efficient trajectory-based algorithm for model order reduction of nonlinear systems via localized projection and global interpolation.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015
Automated Technology Migration Methodology for Mixed-Signal Circuit Based on Multistart Optimization Framework.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Analog circuit performance bound estimation based on extreme value theory.
Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015

Layout decomposition co-optimization for hybrid e-beam and multiple patterning lithography.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2013
Near-Field Communication Transceiver System Modeling and Analysis Using SystemC/SystemC-AMS With the Consideration of Noise Issues.
IEEE Trans. Very Large Scale Integr. Syst., 2013

An Efficient Optimization Based Method to Evaluate the DRV of SRAM Cells.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013

Cumulative Probability Distribution Model for Evaluating User Behavior Prediction Algorithms.
Proceedings of the International Conference on Social Computing, SocialCom 2013, 2013

An Adaptive Social Influence Propagation Model Based on Local Network Topology.
Proceedings of the E-Commerce and Web Technologies - 14th International Conference, 2013

Design automation of analog circuit considering the process variations.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

A parallel sparse linear system solver for large-scale circuit simulation based on Schur Complement.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

Oscillator phase noise verification accounting for process variations.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

FMSSQP: An efficient global optimization tool for the robust design of Rail-to-Rail Op-Amp.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

A practical method for auto-design and optimization of DC-DC buck converter.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

Mixed-signal system verification by SystemC/SystemC-AMS and HSIM-VCS in near field communication tag design.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

2012
An Efficient Method for Evaluating Analog Circuit Performance Bounds Under Process Variations.
IEEE Trans. Circuits Syst. II Express Briefs, 2012

Performance Analysis of Flow-Based Traffic Splitting Strategy on Cluster-Mesh Sensor Networks.
Int. J. Distributed Sens. Networks, 2012

A context-aware computing mediated dynamic service composition and reconfiguration for ubiquitous environment.
Proceedings of the 3rd IEEE International Conference on the Internet of Things, 2012

2011
A Fast Analog Circuit Analysis Algorithm for Design Modification and Verification.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Modeling and analysis of Rayleigh fading channels using stochastic network calculus.
Proceedings of the 2011 IEEE Wireless Communications and Networking Conference, 2011

Worst case analysis for evaluating VLSI circuit performance bounds using an optimization method.
Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011

A novel approach to estimate the impact of analog circuit performance based on the small signal model under process variations.
Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011

Stochastic coverage in event-driven sensor networks.
Proceedings of the IEEE 22nd International Symposium on Personal, 2011

An optimized mapping algorithm based on Simulated Annealing for regular NoC architecture.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

2010
Implementations of FFT and STBD for MIMO-OFDM on a Reconfigurable Baseband Platform.
IEICE Trans. Inf. Syst., 2010

Stochastic Sparse-Grid Collocation Algorithm for Steady-State Analysis of Nonlinear System with Process Variations.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010

A Folding Strategy for SAT solvers based on Shannon's expansion theorem.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

2009
Analytical Evaluation of Retransmission Schemes in Wireless Sensor Networks.
Proceedings of the 69th IEEE Vehicular Technology Conference, 2009

Incremental Circuit Simulation Analysis for Design Modification and Verification.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2008
PER performance enhancement through antenna and transceiver co-design for multi-band OFDM UWB communication.
Proceedings of the 2008 IEEE International Symposium on System-on-Chip, 2008

Low noise amplifier architecture analysis for UWB system.
Proceedings of the 2008 IEEE International Symposium on System-on-Chip, 2008

Foundational-circuit-based spice simulation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

An Efficient Multi-protocol RFID Interrogator Baseband Processor based on a Reconfigurable Architecture.
Proceedings of the International Conference on Embedded Software and Systems, 2008

A current shaping technique to lower phase noise in LC oscillators.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

2007
A Novel Optimization Method for Parametric Yield: Uniform Design Mapping Distance Algorithm.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Solving SAT problem by heuristic polarity decision-making algorithm.
Sci. China Ser. F Inf. Sci., 2007

RLCSYN: RLC Equivalent Circuit Synthesis for Structure-Preserved Reduced-order Model of Interconnect.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Traffic Splitting with Network Calculus for Mesh Sensor Networks.
Proceedings of the Future Generation Communication and Networking, 2007

A sparse grid based spectral stochastic collocation method for variations-aware capacitance extraction of interconnects under nanometer process technology.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Stochastic Sparse-grid Collocation Algorithm (SSCA) for Periodic Steady-State Analysis of Nonlinear System with Process Variations.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006
LVS verification across multiple power domains for a quad-core microprocessor.
ACM Trans. Design Autom. Electr. Syst., 2006

A one-shot projection method for interconnects with process variations.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Time domain model order reduction by wavelet collocation method.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

A Spectral Stochastic Collocation Method for Capacitance Extraction of Interconnects with Process Variations.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

2005
Power-optimal simultaneous buffer insertion/sizing and wire sizing for two-pin nets.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Design and Verification of High-Speed VLSI Physical Design.
J. Comput. Sci. Technol., 2005

Integrating advanced reasoning into a SAT solver.
Sci. China Ser. F Inf. Sci., 2005

Phase noise spectra analysis for LC oscillators.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Power-optimal simultaneous buffer insertion/sizing and uniform wire sizing for single long wires.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A novel wavelet method for noise analysis of nonlinear circuits.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Block SAPOR: block Second-order Arnoldi method for Passive Order Reduction of multi-input multi-output RCS interconnect circuits.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
Automated Architectural Optimization of Digital FIR Filters.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

A closed-form phase noise solution for an ideal LC oscillator.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Frequency domain wavelet method with GMRES for large-scale linear circuit simulation.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Two-sided projection method in variational equation model order reduction of nonlinear circuits.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Frequency driven repeater insertion for deep submicron.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

SAPOR: second-order Arnoldi method for passive order reduction of RCS circuits.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

Steady-State Analysis of Nonlinear Circuits Using Discrete Singular Convolution Method.
Proceedings of the 2004 Design, 2004

Direct Nonlinear Order Reduction with Variational Analysis.
Proceedings of the 2004 Design, 2004

Analog circuit behavioral modeling via wavelet collocation method with auto-companding.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

Satisfiability and integer programming as complementary tools.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003
An error distribution based nonlinear companding method for analog behavioral modeling via wavelet approximation.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

An efficient Sylvester equation solver for time domain circuit simulation by wavelet collocation method.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Power-Optimal Simultaneous Buffer Insertion/Sizing and Wire Sizing.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

2002
Wavelet method for high-speed clock tree simulation.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

A DSP-based turbo codec for 3G communication systems.
Proceedings of the IEEE International Conference on Acoustics, 2002

2001
An efficient balanced truncation realization algorithm for interconnect model order reduction.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Automatic clock tree design with IPs in the system.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Behavioral Modeling of Analog Circuits by Wavelet Collocation Method.
Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

2000
Wire space estimation and routability analysis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

Efficient implementation of a planar clock routing with thetreatment of obstacles.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

Parasitic and mismatch modeling for optimal stack generation [in CMOS].
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

1999
An automatic clock tree design system for high-speed VLSI designs: planar clock routing with the treatment of obstacles.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

1997
Minimization of chip size and power consumption of high-speed VLSI buffers.
Proceedings of the 1997 International Symposium on Physical Design, 1997

1995
Optimization of VLSI Allocation.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

1993
A Two-pole Circuit Model for VLSI High-speed Interconnection.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

Propagation Delay in RLC Interconnection Networks.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

Neighbour State Transition Method for VLSI Optimization Problems.
Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993

Performance-Driven Interconnect Design Based on Distributed RC Delay Model.
Proceedings of the 30th Design Automation Conference. Dallas, 1993

1990
An optimum channel routing algorithm in the restricted wire overlap model.
Integr., 1990

1989
Routing in general junctions.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989


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