Jinho Han
Orcid: 0000-0002-0655-320X
According to our database1,
Jinho Han
authored at least 21 papers
between 2000 and 2024.
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Bibliography
2024
A 6.4Gb/s/pin HBM3 Digital PHY with Low-Power, Area-Efficient Techniques for Chiplet-Based AI processors in 12-nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2024
2023
Proceedings of the 20th International SoC Design Conference, 2023
2.5D Large-Scale Interposer Bonding Process Verification using Daisy-Chain for PIM Heterogeneous Integration Platform.
Proceedings of the International Conference on Electronics, Information, and Communication, 2023
Proceedings of the International Conference on Electronics, Information, and Communication, 2023
2022
Backward Graph Construction and Lowering in DL Compiler for Model Training on AI Accelerators.
Proceedings of the 19th International SoC Design Conference, 2022
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022
M3FPU: Multiformat Matrix Multiplication FPU Architectures for Neural Network Computations.
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022
2021
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
HPC LINPACK Parameter Optimization on Homo-/Heterogeneous System of ARM Neoverse N1SDP.
Proceedings of the HPC Asia 2021: The International Conference on High Performance Computing in Asia-Pacific Region, 2021
2019
Proceedings of the 2019 International SoC Design Conference, 2019
Implementation of Yolo-v2 Image Recognition and Other Testbenches for a CNN Accelerator.
Proceedings of the 9th IEEE International Conference on Consumer Electronics, 2019
Proceedings of the IEEE International Conference on Artificial Intelligence Circuits and Systems, 2019
2017
A 103.125-Gb/s Reverse Gearbox IC in 40-nm CMOS for Supporting Legacy 10- and 40-GbE Links.
IEEE J. Solid State Circuits, 2017
A 1GHz fault tolerant processor with dynamic lockstep and self-recovering cache for ADAS SoC complying with ISO26262 in automotive electronics.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017
2016
A 4×10-Gb/s Referenceless-and-Masterless Phase Rotator-Based Parallel Transceiver in 90-nm CMOS.
IEEE Trans. Very Large Scale Integr. Syst., 2016
A fault tolerant cache system of automotive vision processor complying with ISO26262.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
2015
IEEE J. Solid State Circuits, 2015
2014
0.6-2.7-Gb/s Referenceless Parallel CDR With a Stochastic Dispersion-Tolerant Frequency Acquisition Technique.
IEEE Trans. Very Large Scale Integr. Syst., 2014
2012
Analysis of a Frequency Acquisition Technique With a Stochastic Reference Clock Generator.
IEEE Trans. Circuits Syst. II Express Briefs, 2012
2000
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000