Jaehyeok Yang

Orcid: 0000-0003-0199-3756

According to our database1, Jaehyeok Yang authored at least 16 papers between 2012 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
13.1 A 35.4Gb/s/pin 16Gb GDDR7 with a Low-Power Clocking Architecture and PAM3 IO Circuitry.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024

2022
A 24-Gb/s/Pin 8-Gb GDDR6 With a Half-Rate Daisy-Chain-Based Clocking Architecture and I/O Circuitry for Low-Noise Operation.
IEEE J. Solid State Circuits, 2022

2021
A 24Gb/s/pin 8Gb GDDR6 with a Half-Rate Daisy-Chain-Based Clocking Architecture and IO Circuitry for Low-Noise Operation.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

2020
A Framed-Pulsewidth Modulation Transceiver for High-Speed Broadband Communication Links.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020

2019
Reference-Less Time-Division Duplex Transceiver IC for a Renal Denervation System.
IEEE J. Solid State Circuits, 2019

2018
A 28Gb/s transceiver with chirp-managed EDC for DML systems.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

A 20Gb/s transceiver with framed-pulsewidth modulation in 40nm CMOS.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

A Reference-Less Time-Division-Duplex Transceiver IC for a 5-Fr 6-Electrode Renal Denervation Catheter in 0.18-μm 70-V BCDMOS.
Proceedings of the 40th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2018

2017
A 2.048 Mb/s Full-Duplex Free-Space Optical Transceiver IC for a Real-Time In Vivo Brain-Computer Interface Mouse Experiment Under Social Interaction.
IEEE J. Solid State Circuits, 2017

2016
A 4×10-Gb/s Referenceless-and-Masterless Phase Rotator-Based Parallel Transceiver in 90-nm CMOS.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Time-Divided Spread-Spectrum Code-Based 400 fW-Detectable Multichannel fNIRS IC for Portable Functional Brain Imaging.
IEEE J. Solid State Circuits, 2016

A 2.048 Mb/s full-duplex free-space optical transceiver IC for a real-time in vivo neurofeedback mouse experiment under social interaction.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

2015
11.1 A time-divided spread-spectrum code based 15pW-detectable multi-channel fNIRS IC for portable functional brain imaging.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2014
Phase-Rotator-Based All-Digital Phase-Locked Loop for a Spread-Spectrum Clock Generator.
IEEE Trans. Circuits Syst. II Express Briefs, 2014

8.1 A 6Gb/s transceiver with a nonlinear electronic dispersion compensator for directly modulated distributed-feedback lasers.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2012
Analysis of a Frequency Acquisition Technique With a Stochastic Reference Clock Generator.
IEEE Trans. Circuits Syst. II Express Briefs, 2012


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