Nuno Horta

Affiliations:
  • Instituto de Telecomunicaçoes, Portugal


According to our database1, Nuno Horta authored at least 137 papers between 1994 and 2022.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Online presence:

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Bibliography

2022
DeepPlacer: A custom integrated OpAmp placement tool using deep models.
Appl. Soft Comput., 2022

2021
Shortening the gap between pre- and post-layout analog IC performance by reducing the LDE-induced variations with multi-objective simulated quantum annealing.
Eng. Appl. Artif. Intell., 2021

Hierarchical Yield-Aware Synthesis Methodology Covering Device-, Circuit-, and System-Level for Radiofrequency ICs.
IEEE Access, 2021

Late Breaking Results: Attention in Graph2Seq Neural Networks towards Push-Button Analog IC Placement.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2020
A Folded Voltage-Combiners Biased Amplifier for Low Voltage and High Energy-Efficiency Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

Design of a 4.2-to-5.1 GHz Ultralow-Power Complementary Class-B/C Hybrid-Mode VCO in 65-nm CMOS Fully Supported by EDA Tools.
IEEE Trans. Circuits Syst., 2020

FUZYE: A Fuzzy <i>c</i>-Means Analog IC Yield Optimization Using Evolutionary-Based Algorithms.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Sub-μW Tow-Thomas based biquad filter with improved gain for biomedical applications.
Microelectron. J., 2020

A new family of CMOS inverter-based OTAs for biomedical and healthcare applications.
Integr., 2020

Enhancing a Pairs Trading strategy with the application of Machine Learning.
Expert Syst. Appl., 2020

Ready-to-Fabricate RF Circuit Synthesis Using a Layout- and Variability-Aware Optimization-Based Methodology.
IEEE Access, 2020

Semi-Supervised Artificial Neural Networks towards Analog IC Placement Recommender.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Analog IC Placement Generation via Neural Networks from Unlabeled Data
Springer, ISBN: 978-3-030-50060-3, 2020

2019
Many-Objective Sizing Optimization of a Class-C/D VCO for Ultralow-Power IoT and Ultralow-Phase-Noise Cellular Applications.
IEEE Trans. Very Large Scale Integr. Syst., 2019

Two-Step RF IC Block Synthesis With Preoptimized Inductors and Full Layout Generation In-the-Loop.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Multi-objective framework for cost-effective OTN switch placement using NSGA-II with embedded domain knowledge.
Appl. Soft Comput., 2019

A Low Noise CMOS Inverter-Based OTA for and Healthcare Signal Receivers.
Proceedings of the 16th International Conference on Synthesis, 2019

Synthesis of mm-Wave circuits using-EM-simulated passive structure libraries.
Proceedings of the 16th International Conference on Synthesis, 2019

Artificial Neural Networks as an Alternative for Automatic Analog IC Placement.
Proceedings of the 16th International Conference on Synthesis, 2019

Using Polynomial Regression and Artificial Neural Networks for Reusable Analog IC Sizing.
Proceedings of the 16th International Conference on Synthesis, 2019

On the Exploration of Design Tradeoffs in Analog IC Placement with Layout-dependent Effects.
Proceedings of the 16th International Conference on Synthesis, 2019

Using EDA Tools to Push the Performance Boundaries of an Ultralow-Power IoT-VCO at 65nm.
Proceedings of the 16th International Conference on Synthesis, 2019

Hard and Soft Constraints for Multi-objective Analog IC Sizing Optimization.
Proceedings of the 16th International Conference on Synthesis, 2019

2018
Single-Stage OTA Biased by Voltage-Combiners With Enhanced Performance Using Current Starving.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

Single-Stage Amplifier Biased by Voltage Combiners With Gain and Energy-Efficiency Enhancement.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

Centralized Unmanned Aerial Vehicle Mesh Network Placement Scheme: A Multi-Objective Evolutionary Algorithm Approach.
Sensors, 2018

Enhanced systematic design of a voltage controlled oscillator using a two-step optimization methodology.
Integr., 2018

Guest Editorial Special Issue on Selected Papers from PRIME 2017 and SMACD 2017.
Integr., 2018

Second-order compensation BGR with low TC and high performance for space applications.
Integr., 2018

Parallel SAX/GA for financial pattern matching using NVIDIA's GPU.
Expert Syst. Appl., 2018

Currency exchange prediction using machine learning, genetic algorithms and technical analysis.
CoRR, 2018

Reinforcement learning applied to Forex trading.
Appl. Soft Comput., 2018

Combining Support Vector Machine with Genetic Algorithms to optimize investments in Forex markets with high leverage.
Appl. Soft Comput., 2018

Handling the Effects of Variability and Layout Parasitics in the Automatic Synthesis of LNAs.
Proceedings of the 15th International Conference on Synthesis, 2018

A 20 DB Gain Two-Stage Low-Noise Amplifier with High Yield for 5 GHz Applications.
Proceedings of the 15th International Conference on Synthesis, 2018

On the Exploration of Promising Analog IC Designs via Artificial Neural Networks.
Proceedings of the 15th International Conference on Synthesis, 2018

Design and Optimization of a Class-C/D VCO for Ultra-Low-Power IoT and Cellular Applications.
Proceedings of the 15th International Conference on Synthesis, 2018

11.7b Time-To-Digital Converter with 0.82ps resolution in 130nm CMOS Technology.
Proceedings of the 14th Conference on Ph.D. Research in Microelectronics and Electronics, 2018

An Integrated LC Oscillator with Self Compensation for Frequency Drift and PVT Corners Variations.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

Enhanced analog and RF IC sizing methodology using PCA and NSGA-II optimization kernel.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017
Stochastic-based placement template generator for analog IC layout-aware synthesis.
Integr., 2017

Introduction to the special issue on PRIME 2016 and SMACD 2016.
Integr., 2017

Company event popularity for financial markets using Twitter and sentiment analysis.
Expert Syst. Appl., 2017

Systematic design of a voltage controlled oscillator using a layout-aware approach.
Proceedings of the 14th International Conference on Synthesis, 2017

Layout-aware challenges and a solution for the automatic synthesis of radio-frequency IC blocks.
Proceedings of the 14th International Conference on Synthesis, 2017

New mapping strategies for pre-optimized inductor sets in bottom-up RF IC sizing optimization.
Proceedings of the 14th International Conference on Synthesis, 2017

Design of a BGR Suitable for the Space Industry with Performance of 1.25 V with 0.758 ppm/°C TC from - 55° to 125°C.
Proceedings of the New Generation of CAS, 2017

Efficient yield optimization method using a variable K-Means algorithm for analog IC sizing.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Automatic technology migration of analog IC designs using generic cell libraries.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Using sentiment from Twitter optimized by Genetic Algorithms to predict the stock market.
Proceedings of the 2017 IEEE Congress on Evolutionary Computation, 2017

2016
Logarithmic AD Converter With Selectable Transfer Characteristic.
IEEE Trans. Circuits Syst. II Express Briefs, 2016

Automatic synthesis of RF front-end blocks using multi-objective evolutionary techniques.
Integr., 2016

Design and application of a CMOS active inductor at Ku band based on a multi-objective optimizer.
Integr., 2016

Current-flow and current-density-aware multi-objective optimization of analog IC placement.
Integr., 2016

AIDA: Layout-aware analog circuit-level sizing with in-loop layout generation.
Integr., 2016

Introduction to the special issue on SMACD 2015.
Integr., 2016

A Novel Approach for Optimization in Dynamic Environments Based on Modified Artificial Fish Swarm Algorithm.
Int. J. Comput. Intell. Appl., 2016

Multi-objective kernel mapping and scheduling for morphable many-core architectures.
Expert Syst. Appl., 2016

Combining rules between PIPs and SAX to identify patterns in financial markets.
Expert Syst. Appl., 2016

SCALES: A high speed simulator tool for pipeline A/D converters.
Proceedings of the 13th International Conference on Synthesis, 2016

Automated analog IC design constraints generation for a layout-aware sizing approach.
Proceedings of the 13th International Conference on Synthesis, 2016

Yield optimization using k-means clustering algorithm to reduce Monte Carlo simulations.
Proceedings of the 13th International Conference on Synthesis, 2016

On-the-fly exploration of placement templates for analog IC layout-aware sizing methodologies.
Proceedings of the 13th International Conference on Synthesis, 2016

Design automation tasks scheduling for enhanced parallel execution of a state-of-the-art layout-aware sizing approach.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015
Floorplan-aware analog IC sizing and optimization based on topological constraints.
Integr., 2015

A hybrid approach to portfolio composition based on fundamental and technical indicators.
Expert Syst. Appl., 2015

Boosting Trading Strategies performance using VIX indicator together with a dual-objective Evolutionary Computation optimizer.
Expert Syst. Appl., 2015

Multi-objective optimization of analog integrated circuit placement hierarchy in absolute coordinates.
Expert Syst. Appl., 2015

A multi-objective routing algorithm for Wireless Multimedia Sensor Networks.
Appl. Soft Comput., 2015

A voltage-combiners-biased amplifier with enhanced gain and speed using current starving.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Extraction and application of wiring symmetry rules to route analog multiport terminals.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Thermal-aware floorplanning and layout generation of MOSFET power stages.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Developing Multi-Time Frame Trading Rules with a Trend Following Strategy, using GA.
Proceedings of the Genetic and Evolutionary Computation Conference, 2015

Layout-aware sizing of analog ICs using floorplan & routing estimates for parasitic extraction.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014
A survey on nonlinear analog-to-digital converters.
Integr., 2014

Electromigration-aware analog Router with multilayer multiport terminal structures.
Integr., 2014

LC-VCO automatic synthesis using multi-objective evolutionary techniques.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Multi-objective Optimization of Investment Strategies - Based on Evolutionary Computation Techniques, in Volatile Environments.
Proceedings of the ICEIS 2014, 2014

A rad-hard DC-DC converter controller.
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

Logarithmic AD conversion using latched comparators and a time-to-digital converter.
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

A cascode-free single-stage amplifier using a fully-differential folded voltage-combiner.
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

Automatic layout generation of power MOSFET transistors in bulk CMOS.
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

Electromigration-aware and IR-Drop avoidance routing in analog multiport terminal structures.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Portfolio optimization using fundamental indicators based on multi-objective EA.
Proceedings of the IEEE Conference on Computational Intelligence for Financial Engineering & Economics, 2014

2013
LAYGEN II - Automatic Layout Generation of Analog Integrated Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

A SAX-GA approach to evolve investment strategies on financial markets based on pattern discovery techniques.
Expert Syst. Appl., 2013

Single-stage amplifiers with gain enhancement and improved energy-efficiency employing voltage-combiners.
Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013

Enhancing a Layout-Aware Synthesis Methodology for Analog ICs by Embedding Statistical Knowledge into the Evolutionary Optimization Kernel.
Proceedings of the Technological Innovation for the Internet of Things, 2013

Optimizing investment strategies based on companies earnings using genetic algorithms.
Proceedings of the Genetic and Evolutionary Computation Conference, 2013

Multi-dimensional pattern discovery in financial time series using sax-ga with extended robustness.
Proceedings of the Genetic and Evolutionary Computation Conference, 2013

A new metaheuristc combining gradient models with NSGA-II to enhance analog IC synthesis.
Proceedings of the IEEE Congress on Evolutionary Computation, 2013

Multi-port multi-terminal analog router based on an evolutionary optimization kernel.
Proceedings of the IEEE Congress on Evolutionary Computation, 2013

2012
Solving a Capacitated Exam Timetabling Problem Instance Using a Bi-objective NSGA-II.
Proceedings of the Computational Intelligence - International Joint Conference, 2012

Solving an Uncapacitated Exam Timetabling Problem Instance using a Hybrid NSGA-II.
Proceedings of the IJCCI 2012 - Proceedings of the 4th International Joint Conference on Computational Intelligence, Barcelona, Spain, 5, 2012

An evolutionary approach to define investment strategies based on macroeconomic indicators and VIX data.
Proceedings of the Genetic and Evolutionary Computation Conference, 2012

Automated passive filter design using multi-objective genetic algorithms with variable parameters.
Proceedings of the Genetic and Evolutionary Computation Conference, 2012

LAYGEN II: automatic analog ICs layout generator based on a template approach.
Proceedings of the Genetic and Evolutionary Computation Conference, 2012

GENOM-POF: multi-objective evolutionary synthesis of analog ICs with corners validation.
Proceedings of the Genetic and Evolutionary Computation Conference, 2012

A new SAX-GA methodology applied to investment strategies optimization.
Proceedings of the Genetic and Evolutionary Computation Conference, 2012

2011
Applying a GA kernel on optimizing technical analysis rules for stock picking and portfolio composition.
Expert Syst. Appl., 2011

Optimal OpAmp sizing based on a fuzzy-genetic kernel.
Proceedings of the 13th Annual Genetic and Evolutionary Computation Conference, 2011

Fitness function evaluation for MA trading strategies based on genetic algorithms.
Proceedings of the 13th Annual Genetic and Evolutionary Computation Conference, 2011

Overcurrent detection circuit for integrated class-D amplifiers.
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011

Trading with optimized uptrend and downtrend pattern templates using a genetic algorithm kernel.
Proceedings of the IEEE Congress on Evolutionary Computation, 2011

2010
Analog Circuits and Systems Optimization based on Evolutionary Computation Techniques
Studies in Computational Intelligence 294, Springer, ISBN: 978-3-642-12345-0, 2010

Analog circuits optimization based on evolutionary computation techniques.
Integr., 2010

An Innovative GA Optimized Investment Strategy based on a New Technical Indicator using Multiple MAS.
Proceedings of the ICEC 2010 - Proceedings of the International Conference on Evolutionary Computation, [part of the International Joint Conference on Computational Intelligence IJCCI 2010], Valencia, Spain, October 24, 2010

Trading in financial markets using pattern recognition optimized by genetic algorithms.
Proceedings of the Genetic and Evolutionary Computation Conference, 2010

2009
Reconfigurable multi-mode sigma-delta modulator for 4G mobile terminals.
Integr., 2009

FUGA: a fuzzy-genetic analog circuit optimization kernel.
Proceedings of the Genetic and Evolutionary Computation Conference, 2009

Using GAs to balance technical indicators on stock picking for financial portfolio composition.
Proceedings of the Genetic and Evolutionary Computation Conference, 2009

Enhancing analog IC design optimization kernels with simple fuzzy models.
Proceedings of the 19th European Conference on Circuit Theory and Design, 2009

2008
A reconfigurable A/D converter for 4G wireless systems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Overview of radiation effects and design constraints off fully custom SMPS.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2007
GA-SVM feasibility model and optimization kernel applied to analog IC design automation.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

Automatic analog IC layout generation based on a evolutionary computation approach.
Proceedings of the Genetic and Evolutionary Computation Conference, 2007

Design of a multimode reconfigurable sigma-delta converter for 4G wireless receivers.
Proceedings of the 18th European Conference on Circuit Theory and Design, 2007

An evolutionary optimization kernel using a dynamic GA-SVM model applied to analog IC design.
Proceedings of the 18th European Conference on Circuit Theory and Design, 2007

2006
AIDA: Analog IC Design Automation based on a Fully Configurable Design Hierarchy and Flow.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

GA-SVM Optimization Kernel applied to Analog IC Design Automation.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

2005
Laygen - An evolutionary approach to automatic analog IC layout generation.
Proceedings of the 12th IEEE International Conference on Electronics, 2005

Fuzzy Chess Tactics.
Proceedings of the Joint 4th Conference of the European Society for Fuzzy Logic and Technology and the 11th Rencontres Francophones sur la Logique Floue et ses Applications, 2005

2004
Enhancing the SCORM metadata model.
Proceedings of the 13th international conference on World Wide Web, 2004

Enhancing the SCORM Modelling Scope.
Proceedings of the IEEE International Conference on Advanced Learning Technologies, 2004

A Multi-Level Model for Tracking Analysis in E-Learning Platforms.
Proceedings of the IEEE International Conference on Advanced Learning Technologies, 2004

2003
Enhanced genetic algorithm kernel applied to a circuit-level optimization E-design environment.
Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003

VIANET - A New Web Framework for Distance Learning.
Proceedings of the 2003 IEEE International Conference on Advanced Learning Technologies, 2003

A New Approach towards E-Learning Content Standardization and Enhanced Usability.
Proceedings of the IADIS International Conference WWW/Internet 2003, 2003

2002
GENOM: circuit-level optimizer based on a modified genetic algorithm kernel.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Towards a Framework for Semantic Service Discovery in Ubiquitous P2P Enviroments.
Proceedings of the International Conference on Internet Computing, 2002

2001
IC design automation from circuit level optimization to retargetable layout.
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

A Skill-based library for retargetable embedded analog cores.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

2000
Symbolic techniques applied to switched-current ADCs synthesis.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

1999
RAPID-retargetability for reusability of application-driven quadrature D/A interface block design.
Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999

1998
Symbolic synthesis of non-linear data converters.
Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998

1997
Algorithm-driven synthesis of data conversion architectures.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

1994
A Methodology for Automatic Generation of Data Conversion Topologies from Algorithms.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994


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