Jason Lowe-Power

Orcid: 0000-0002-8880-8703

Affiliations:
  • University of California, Davis, USA
  • University of Wisconsin - Madison, USA (former)


According to our database1, Jason Lowe-Power authored at least 34 papers between 2013 and 2023.

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Bibliography

2023
Prediction of organic compound aqueous solubility using machine learning: a comparison study of descriptor-based and fingerprints-based models.
J. Cheminformatics, December, 2023

Aragorn: A Privacy-Enhancing System for Mobile Cameras.
Proc. ACM Interact. Mob. Wearable Ubiquitous Technol., December, 2023

Centauri: Practical Rowhammer Fingerprinting.
CoRR, 2023

A Cycle-level Unified DRAM Cache Controller Model for 3DXPoint Memory Systems in gem5.
CoRR, 2023

Efficient Large Scale DLRM Implementation on Heterogeneous Memory Systems.
Proceedings of the High Performance Computing - 38th International Conference, 2023

Scalable Hardware Acceleration of Graph Processing with Photonic Interconnects.
Proceedings of the International Conference on Photonics in Switching and Computing, 2023

Enabling Design Space Exploration of DRAM Caches for Emerging Memory Systems.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2023

2022
A Model for Scalable and Balanced Accelerators for Graph Processing.
IEEE Comput. Archit. Lett., 2022

LLM: Realizing Low-Latency Memory by Exploiting Embedded Silicon Photonics for Irregular Workloads.
Proceedings of the High Performance Computing - 37th International Conference, 2022

SoK: Limitations of Confidential Computing via TEEs for High-Performance Compute Systems.
Proceedings of the 2022 IEEE International Symposium on Secure and Private Execution Environment Design (SEED), 2022

2021
HTA: A Scalable High-Throughput Accelerator for Irregular HPC Workloads.
Proceedings of the High Performance Computing - 36th International Conference, 2021

A Case Against Hardware Managed DRAM Caches for NVRAM Based Systems.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2021

Enabling Reproducible and Agile Full-System Simulation.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2021

Performance Analysis of Scientific Computing Workloads on General Purpose TEEs.
Proceedings of the 35th IEEE International Parallel and Distributed Processing Symposium, 2021

Stream Floating: Enabling Proactive and Decentralized Cache Optimizations.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2021

2020
The Tribes of Machine Learning and the Realm of Computer Architecture.
CoRR, 2020

Performance Analysis of Scientific Computing Workloads on Trusted Execution Environments.
CoRR, 2020

The gem5 Simulator: Version 20.0+.
CoRR, 2020

Difficulty and self-efficacy: An exploratory study.
Br. J. Educ. Technol., 2020

HCAPP: Scalable Power Control for Heterogeneous 2.5D Integrated Systems.
Proceedings of the ICPP 2020: 49th International Conference on Parallel Processing, 2020

AutoTM: Automatic Tensor Movement in Heterogeneous Memory Systems using Integer Linear Programming.
Proceedings of the ASPLOS '20: Architectural Support for Programming Languages and Operating Systems, 2020

2019
The Davis In-Order (DINO) CPU: A Teaching-focused RISC-V CPU Design.
Proceedings of the Workshop on Computer Architecture Education, 2019

Enabling scalable chiplet-based uniform memory architectures with silicon photonics.
Proceedings of the International Symposium on Memory Systems, 2019

FlexCPU: A Configurable Out-of-Order CPU Abstraction.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2019

2018
A case for exposing extra-architectural state in the ISA: position paper.
Proceedings of the 7th International Workshop on Hardware and Architectural Support for Security and Privacy, 2018

Improving Provisioned Power Efficiency in HPC Systems with GPU-CAPP.
Proceedings of the 25th IEEE International Conference on High Performance Computing, 2018

Filtering Translation Bandwidth with Virtual Caching.
Proceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems, 2018

2016
When to use 3D Die-Stacked Memory for Bandwidth-Constrained Big Data Workloads.
CoRR, 2016

2015
Implications of Emerging 3D GPU Architecture on the Scan Primitive.
SIGMOD Rec., 2015

gem5-gpu: A Heterogeneous CPU-GPU Simulator.
IEEE Comput. Archit. Lett., 2015

Border control: sandboxing accelerators.
Proceedings of the 48th International Symposium on Microarchitecture, 2015

Toward GPUs being mainstream in analytic processing: An initial argument using simple scan-aggregate queries.
Proceedings of the 11th International Workshop on Data Management on New Hardware, 2015

2014
Supporting x86-64 address translation for 100s of GPU lanes.
Proceedings of the 20th IEEE International Symposium on High Performance Computer Architecture, 2014

2013
Heterogeneous system coherence for integrated CPU-GPU systems.
Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture, 2013


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