John Safran

According to our database1, John Safran authored at least 5 papers between 2003 and 2015.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2015
Impact of 3D copper TSV integration on 32SOI FEOL and BEOL reliability.
Proceedings of the IEEE International Reliability Physics Symposium, 2015

2013
Field Tolerant Dynamic Intrinsic Chip ID Using 32 nm High-K/Metal Gate SOI Embedded DRAM.
J. Solid-State Circuits, 2013

2008
A Commercial Field-Programmable Dense eFUSE Array Memory with 99.999% Sense Yield for 45nm SOI CMOS.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

2007
Electrically Programmable Fuse (eFUSE): From Memory Redundancy to Autonomic Chips.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2003
A power-optimized widely-tunable 5-GHz monolithic VCO in a digital SOI CMOS technology on high resistivity substrate.
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003


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