Jean-Olivier Plouchart
According to our database1,
Jean-Olivier Plouchart
authored at least 43 papers
between 1999 and 2023.
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Bibliography
2023
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
2022
A 24-30-GHz 256-Element Dual-Polarized 5G Phased Array Using Fast On-Chip Beam Calculators and Magnetoelectric Dipole Antennas.
IEEE J. Solid State Circuits, 2022
A 24-to-30GHz 256-Element Dual-Polarized 5G Phased Array with Fast Beam-Switching Support for >30, 000 Beams.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
2020
A 250-mW 60-GHz CMOS Transceiver SoC Integrated With a Four-Element AiP Providing Broad Angular Link Coverage.
IEEE J. Solid State Circuits, 2020
2018
Fully Integrated 94-GHz Dual-Polarized TX and RX Phased Array Chipset in SiGe BiCMOS Operating up to 105 °C.
IEEE J. Solid State Circuits, 2018
Proceedings of the 2018 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS), 2018
2017
An ultra-high bandwidth sub-ranging ADC with programmable dynamic range in 32nm CMOS SOI.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017
2015
Co-Learning Bayesian Model Fusion: Efficient Performance Modeling of Analog and Mixed-Signal Circuits Using Side Information.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015
2014
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
IEEE Des. Test, 2014
2013
IEEE Trans. Circuits Syst. I Regul. Pap., 2013
IEEE J. Solid State Circuits, 2013
IEEE J. Solid State Circuits, 2013
Indirect performance sensing for on-chip analog self-healing via Bayesian model fusion.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013
2012
An integral path self-calibration scheme for a 20.1-26.7GHz dual-loop PLL in 32nm SOI CMOS.
Proceedings of the Symposium on VLSI Circuits, 2012
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012
2011
IEEE J. Solid State Circuits, 2011
A 4GS/s, 8.45 ENOB and 5.7fJ/conversion, digital assisted, sampling system in 45nm CMOS SOI.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011
2010
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010
2009
Bang-bang digital PLLs at 11 and 20GHz with sub-200fs integrated jitter for high-speed serial communication applications.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009
Proceedings of the IEEE International Solid-State Circuits Conference, 2009
2008
A Modular All-Digital PLL Architecture Enabling Both 1-to-2GHz and 24-to-32GHz Operation in 65nm CMOS.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008
2007
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
A 70GHz Manufacturable Complementary LC-VCO with 6.14GHz Tuning Range in 65nm SOI CMOS.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
A Data-Driven Statistical Approach to Analyzing Process Variation in 65nm SOI Technology.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007
Proceedings of the 44th Design Automation Conference, 2007
2006
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006
CMOS Mixed-Signal Circuit Process Variation Sensitivity Characterization for Yield Improvement.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006
2004
A 4-91-GHz traveling-wave amplifier in a standard 0.12-μm SOI CMOS microprocessor technology.
IEEE J. Solid State Circuits, 2004
A low-voltage 40-GHz complementary VCO with 15% frequency tuning range in SOI CMOS technology.
IEEE J. Solid State Circuits, 2004
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004
2003
IEEE J. Solid State Circuits, 2003
IEEE J. Solid State Circuits, 2003
Application of an SOI 0.12-µm CMOS technology to SoCs with low-power and high-frequency circuits.
IBM J. Res. Dev., 2003
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003
A power-optimized widely-tunable 5-GHz monolithic VCO in a digital SOI CMOS technology on high resistivity substrate.
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003
Proceedings of the ESSCIRC 2003, 2003
A 4-91 GHz distributed amplifier in a standard 0.12 μm SOI CMOS microprocessor technology.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2003
2002
Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, 2002
2000
1999
Proceedings of the IEEE 1999 Custom Integrated Circuits Conference, 1999