Mladen Berekovic
Orcid: 0000-0003-1911-756XAffiliations:
- Braunschweig University of Technology, Germany
According to our database1,
Mladen Berekovic
authored at least 108 papers
between 1997 and 2024.
Collaborative distances:
Collaborative distances:
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Bibliography
2024
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2024
2023
ACM Trans. Reconfigurable Technol. Syst., December, 2023
Proceedings of the 19th International Conference on Wireless and Mobile Computing, 2023
Proceedings of the IEEE Symposium Series on Computational Intelligence, 2023
SystemC Model of Power Side-Channel Attacks Against AI Accelerators: Superstition or not?
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2023
2022
On the Dependability Lifecycle of Electrical/Electronic Product Development: The Dual-Cone V-Model.
Computer, 2022
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
2021
Cryptogr., 2021
Echtzeitfähige Ethernet-Kommunikation in automobilen Multicore-Systemen mit hierarchischem Speicherlayout.
Proceedings of the Echtzeit 2021, 2021
Hardware-Beschleuniger für automobile Multicore-Mikrocontroller mit einer harten Echtzeitanforderung.
Proceedings of the Echtzeit 2021, 2021
Static Allocation of Basic Blocks Based on Runtime and Memory Requirements in Embedded Real-Time Systems with Hierarchical Memory Layout.
Proceedings of the Second Workshop on Next Generation Real-Time Embedded Systems, 2021
A comparative survey of open-source application-class RISC-V processor implementations.
Proceedings of the CF '21: Computing Frontiers Conference, 2021
Clone-Resistant Secured Booting Based on Unknown Hashing Created in Self-Reconfigurable Platform.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2021
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2021
2019
Cache-Kohärenz für embedded Multicore-Mikrocontroller mit harter Echtzeitanforderung.
Proceedings of the Echtzeit 2019 - Autonome Systeme, 2019
MemOpt: Automated Memory Distribution for Multicore Microcontrollers with Hard Real-Time Requirements.
Proceedings of the 2019 IEEE Nordic Circuits and Systems Conference, 2019
2018
Effects of Concurrent Access to Embedded Multicore Microcontrollers with Hard Real-Time Demands.
Proceedings of the 13th IEEE International Symposium on Industrial Embedded Systems, 2018
Proceedings of the International Conference on Field-Programmable Technology, 2018
2017
A Survey of Hardware Technologies for Mixed-Critical Integration Explored in the Project EMC^2.
Proceedings of the Computer Safety, Reliability, and Security, 2017
Proceedings of the International Symposium on Memory Systems, 2017
IR-drop aware Design & technology co-optimization for N5 node with different device and cell height options.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017
Proceedings of the 17th IEEE-RAS International Conference on Humanoid Robotics, 2017
Energy efficient cooperative spectrum sensing in Cognitive Radio Sensor Network Using FPGA: A survey.
Proceedings of the 21st Conference of Open Innovations Association, 2017
2016
ACM Trans. Embed. Comput. Syst., 2016
Proceedings of the IEEE Nordic Circuits and Systems Conference, 2016
Proceedings of the Second International Symposium on Memory Systems, 2016
Towards bridging the gap between academic and industrial heterogeneous system architecture design space exploration.
Proceedings of the 2016 Workshop on Rapid Simulation and Performance Evaluation, 2016
2015
A Comparison of High-Level Design Tools for SoC-FPGA on Disparity Map Calculation Example.
CoRR, 2015
Proceedings of the 2015 International Conference on Embedded Computer Systems: Architectures, 2015
Revealing Potential Performance Improvements by Utilizing Hybrid Work-Sharing for Resource-Intensive Seismic Applications.
Proceedings of the 23rd Euromicro International Conference on Parallel, 2015
High efficient hardware allocation framework of arbitrary inverse transform coding blocks in H.265.
Proceedings of the 2015 International Symposium on Intelligent Signal Processing and Communication Systems, 2015
2014
Proceedings of the 9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip, 2014
Proceedings of the 9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip, 2014
Proceedings of the 22nd Euromicro International Conference on Parallel, 2014
A lightweight-system-level power and area estimation methodology for application specific instruction set processors.
Proceedings of the 24th International Workshop on Power and Timing Modeling, 2014
On RTL to TLM Abstraction to Benefit Simulation Performance and Modeling Productivity in NoC Design Exploration.
Proceedings of the 2014 International Workshop on Network on Chip Architectures, 2014
On the Relevance of Architectural Awareness for Efficient Fork/Join Support on Cluster-Based Manycores.
Proceedings of the 2nd International Workshop on Many-core Embedded Systems, 2014
2013
Proceedings of the IEEE Workshop on Signal Processing Systems, 2013
Safe Virtual Interrupts Leveraging Distributed Shared Resources and Core-to-Core Communication on Many-Core Platforms.
Proceedings of the IEEE 19th Pacific Rim International Symposium on Dependable Computing, 2013
Proceedings of the 19th IEEE International Conference on Parallel and Distributed Systems, 2013
Proceedings of the Architecture of Computing Systems - ARCS 2013, 2013
2012
ACM Trans. Embed. Comput. Syst., 2012
Low-Overhead Barrier Synchronization for OpenMP-like Parallelism on the Single-Chip Cloud Computer.
Proceedings of the Many-core Applications Research Community (MARC) Symposium at RWTH Aachen University, 2012
Proceedings of the 14th International IEEE Symposium on High-Assurance Systems Engineering, 2012
2011
Proceedings of the Recent Advances in the Message Passing Interface, 2011
Proceedings of the 3rd Many-core Applications Research Community (MARC) Symposium. Proceedings of the 3rd MARC Symposium, 2011
2010
J. Signal Process. Syst., 2010
Small-ruleset regular expression matching on GPGPUs: quantitative performance analysis and optimization.
Proceedings of the 24th International Conference on Supercomputing, 2010
Proceedings of the 13th Euromicro Conference on Digital System Design, 2010
Proceedings of the 13th Euromicro Conference on Digital System Design, 2010
Proceedings of the Dynamically Reconfigurable Architectures, 11.07. - 16.07.2010, 2010
2009
J. Signal Process. Syst., 2009
Mapping of nomadic multimedia applications on the ADRES reconfigurable array processor.
Microprocess. Microsystems, 2009
Proceedings of the 2009 Workshop on Embedded Systems Education, 2009
A low-power ASIP for IEEE 802.15.4a ultra-wideband impulse radio baseband processing.
Proceedings of the Design, Automation and Test in Europe, 2009
Low-Power ASIP Architecture Exploration and Optimization for Reed-Solomon Processing.
Proceedings of the 20th IEEE International Conference on Application-Specific Systems, 2009
2008
A Distributed, Simultaneously Multi-Threaded (SMT) Processor with Clustered Scheduling Windows for Scalable DSP Performance.
J. Signal Process. Syst., 2008
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2008
Implementation of an UWB Impulse-Radio Acquisition and Despreading Algorithm on a Low Power ASIP.
Proceedings of the High Performance Embedded Architectures and Compilers, 2008
Proceedings of the High Performance Embedded Architectures and Compilers, 2008
Proceedings of the 5th Conference on Computing Frontiers, 2008
Mapping of the AES cryptographic algorithm on a Coarse-Grain reconfigurable array processor.
Proceedings of the 19th IEEE International Conference on Application-Specific Systems, 2008
2007
Design of 100 muW Wireless Sensor Nodes on Energy Scavengers for Biomedical Monitoring.
Proceedings of the Embedded Computer Systems: Architectures, 2007
Proceedings of the 14th IEEE International Conference on Electronics, 2007
Proceedings of the 2007 5th Workshop on Embedded Systems for Real-Time Multimedia, 2007
Ulta-Low-Power Wireless Sensor Node Design on 100 uW Scavenging Energy for Applications In Biomedical Monitoring.
Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007
Mapping control-intensive video kernels onto a coarse-grain reconfigurable architecture: the H.264/AVC deblocking filter.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007
Proceedings of the Power-aware Computing Systems, 21.01. - 26.01.2007, 2007
Proceedings of the Reconfigurable Computing: Architectures, 2007
Proceedings of the Reconfigurable Computing: Architectures, 2007
2006
Proceedings of the VLSI-SoC: Research Trends in VLSI and Systems on Chip, 2006
A Scalable, Multi-thread, Multi-issue Array Processor Architecture for DSP Applications Based on Extended Tomasulo Scheme.
Proceedings of the Embedded Computer Systems: Architectures, 2006
Proceedings of the Reconfigurable Computing: Architectures and Applications, 2006
2005
Eine skalierbare, verteilte Prozessor-Architektur mit simultanem multi-threading für Anwendungen der digitalen Signalverarbeitung.
PhD thesis, 2005
A Platform-Independent Methodology for Performance Estimation of Multimedia Signal Processing Applications.
J. VLSI Signal Process., 2005
J. VLSI Signal Process., 2005
2004
SIGARCH Comput. Archit. News, 2004
SIGARCH Comput. Archit. News, 2004
2003
HiBRID-SoC: A Multi-Core System-on-Chip Architecture for Multimedia Signal Processing.
Proceedings of the IFIP VLSI-SoC 2003, 2003
Proceedings of the 2003 International Conference on Image Processing, 2003
HiBRID-SoC: A Multi-Core System-on-Chip Architecture for Multimedia Signal Processing Applications.
Proceedings of the 2003 Design, 2003
2002
J. VLSI Signal Process., 2002
IEEE Trans. Circuits Syst. Video Technol., 2002
A platform-independent methodology for performance estimation of streaming media applications.
Proceedings of the 2002 IEEE International Conference on Multimedia and Expo, 2002
2001
Proceedings of the 2001 IEEE International Conference on Multimedia and Expo, 2001
Proceedings of the IEEE International Conference on Acoustics, 2001
2000
Coprocessor architecture for MPEG-4 video object rendering.
Proceedings of the Visual Communications and Image Processing 2000, 2000
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
Proceedings of the 12th IEEE International Conference on Application-Specific Systems, 2000
1999
Hardware Realization of a Java Virtual Machine for High Performance Multimedia Applications.
J. VLSI Signal Process., 1999
J. VLSI Signal Process., 1999
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999
Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999
Hardware Realisierung einer JAVA Virtual Machine für High Performance Multimedia-Anwendungen.
Proceedings of the Architektur von Rechensystemen, Systemarchitektur auf dem Weg ins 3. Jahrtausend: Neue Strukturen, Konzepte, Verfahren und Bewertungsmethoden, 1999
1998
J. VLSI Signal Process., 1998
Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998
Proceedings of the 1998 IEEE International Conference on Acoustics, 1998
Realization of a Programmable Parallel DSP for High Performance Image Processing Applications.
Proceedings of the 35th Conference on Design Automation, 1998
An Array Processor Architecture with Parallel Data Cache for Image Rendering and Compositing.
Proceedings of the Computer Graphics International Conference, 1998
1997
An Algorithm Adapted Autonomous Controlling Concept for a Parallel Single-Chip Digital Signal Processor.
J. VLSI Signal Process., 1997