Jugantor Chetia

According to our database, Jugantor Chetia authored at least 4 papers between 2009 and 2021.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of five.

2021

Seamless Physical Implementation of ASIC Hierarchical Integrated Scan Architecture.

Bambang Suparjo, Jugantor Chetia, Ankit R. Shah

Proceedings of the IEEE International Test Conference, 2021

2009

REDEFINE: Runtime reconfigurable polymorphic ASIC.

Mythri Alle, Keshavan Varadarajan, Alexander Fell, C. Ramesh Reddy, Joseph Nimmy, Saptarsi Das, Prasenjit Biswas, Jugantor Chetia, Adarsha Rao, S. K. Nandy, Ranjani Narayan

ACM Trans. Embed. Comput. Syst., 2009

Generic routing rules and a scalable access enhancement for the Network-on-Chip RECONNECT.

Alexander Fell, Prasenjit Biswas, Jugantor Chetia, S. K. Nandy, Ranjani Narayan

Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009

Streaming FFT on REDEFINE-v2: an application-architecture design space exploration.

Alexander Fell, Mythri Alle, Keshavan Varadarajan, Prasenjit Biswas, Saptarsi Das, Jugantor Chetia, S. K. Nandy, Ranjani Narayan

Proceedings of the 2009 International Conference on Compilers, 2009