Keshavan Varadarajan

According to our database1, Keshavan Varadarajan authored at least 19 papers between 2005 and 2011.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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On csauthors.net:

Bibliography

2011
Data Flow Graph Partitioning Algorithms and Their Evaluations for Optimal Spatio-temporal Computation on a Coarse Grain Reconfigurable Architecture.
IPSJ Trans. Syst. LSI Des. Methodol., 2011

A Method for Flexible Reduction over Binary Fields using a Field Multiplier.
Proceedings of the SECRYPT 2011 - Proceedings of the International Conference on Security and Cryptography, Seville, Spain, 18, 2011

Interconnect-topology independent mapping algorithm for a Coarse Grained Reconfigurable Architecture.
Proceedings of the 2011 International Conference on Field-Programmable Technology, 2011

Dataflow Graph Partitioning for Optimal Spatio-Temporal Computation on a Coarse Grain Reconfigurable Architecture.
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2011

2010
Enhancements for variable N-point streaming FFT/IFFT on REDEFINE, a runtime reconfigurable architecture.
Proceedings of the 2010 International Conference on Embedded Computer Systems: Architectures, 2010

Design space exploration of systolic realization of QR factorization on a runtime reconfigurable platform.
Proceedings of the 2010 International Conference on Embedded Computer Systems: Architectures, 2010

Accelerating multi-core simulators.
Proceedings of the 2010 ACM Symposium on Applied Computing (SAC), 2010

Accelerating Numerical Linear Algebra Kernels on a Scalable Run Time Reconfigurable Platform.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

Towards minimizing execution delays on dynamically reconfigurable processors: a case study on REDEFINE.
Proceedings of the 2010 International Conference on Compilers, 2010

2009
REDEFINE: Runtime reconfigurable polymorphic ASIC.
ACM Trans. Embed. Comput. Syst., 2009

Streaming FFT on REDEFINE-v2: an application-architecture design space exploration.
Proceedings of the 2009 International Conference on Compilers, 2009

Compiling Techniques for Coarse Grained Runtime Reconfigurable Architectures.
Proceedings of the Reconfigurable Computing: Architectures, 2009

2008
Realizing a flexible constraint length Viterbi decoder for software radio on a de Bruijn interconnection network.
Proceedings of the 2008 IEEE International Symposium on System-on-Chip, 2008

RECONNECT: A NoC for polymorphic ASICs using a low overhead single cycle router.
Proceedings of the 19th IEEE International Conference on Application-Specific Systems, 2008

Synthesis of application accelerators on Runtime Reconfigurable Hardware.
Proceedings of the 19th IEEE International Conference on Application-Specific Systems, 2008

2007
REDEFINE: Architecture of a SoC Fabric for Runtime Composition of Computation Structures.
Proceedings of the FPL 2007, 2007

2006
Molecular Caches: A caching structure for dynamic creation of application-specific Heterogeneous cache regions.
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-39 2006), 2006

Framework for Enabling Highly Available Distributed Applications for Utility Computing.
Proceedings of the Parallel and Distributed Processing and Applications, 2006

2005
A Framework for QoS Adaptive Grid Meta Scheduling.
Proceedings of the 16th International Workshop on Database and Expert Systems Applications (DEXA 2005), 2005


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