Ranjani Narayan
According to our database1,
Ranjani Narayan
authored at least 50 papers
between 1990 and 2019.
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Bibliography
2019
Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019
A Systematic Approach for Acceleration of Matrix-Vector Operations in CGRA through Algorithm-Architecture Co-Design.
Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019
2018
Efficient Realization of Householder Transform Through Algorithm-Architecture Co-Design for Acceleration of QR Factorization.
IEEE Trans. Parallel Distributed Syst., 2018
Efficient Realization of Givens Rotation through Algorithm-Architecture Co-design for Acceleration of QR Factorization.
CoRR, 2018
Achieving Efficient Realization of Kalman Filter on CGRA Through Algorithm-Architecture Co-design.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2018
2017
Parallel Process. Lett., 2017
Energy aware synthesis of application kernels through composition of data-paths on a CGRA.
Integr., 2017
REDEFINE<sup>®</sup>™: a case for WCET-friendly hardware accelerators for real time applications (work-in-progress).
Proceedings of the 2017 International Conference on Compilers, 2017
2016
IEEE Trans. Parallel Distributed Syst., 2016
CoRR, 2016
Achieving Efficient QR Factorization by Algorithm-Architecture Co-design of Householder Transformation.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016
Efficient Realization of Table Look-Up Based Double Precision Floating Point Arithmetic.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016
VOP: Architecture of a Processor for Vector Operations in On-Line Learning of Neural Networks.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016
Proceedings of the 7th Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures and the 5th Workshop on Design Tools and Architectures For Multicore Embedded Computing Platforms, 2016
2015
Scalable and Energy Efficient, Dynamically Reconfigurable Fast Fourier Transform Architecture.
J. Low Power Electron., 2015
Router Attack toward NoC-enabled MPSoC and Monitoring Countermeasures against such Threat.
Circuits Syst. Signal Process., 2015
Proceedings of the 28th International Conference on VLSI Design, 2015
Micro-architectural Enhancements in Distributed Memory CGRAs for LU and QR Factorizations.
Proceedings of the 28th International Conference on VLSI Design, 2015
Proceedings of the 28th International Conference on VLSI Design, 2015
A deterministic, minimal routing algorithm for a toroidal, rectangular honeycomb topology using a 2-tupled relative address.
Proceedings of the 28th IEEE International System-on-Chip Conference, 2015
Energy Aware Synthesis of Application Kernels Expressed in Functional Languages on a Coarse Grained Composable Reconfigurable Array.
Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2015
Proceedings of the 17th IEEE International Conference on High Performance Computing and Communications, 2015
2014
A framework for post-silicon realization of arbitrary instruction extensions on reconfigurable data-paths.
J. Syst. Archit., 2014
Proceedings of the 2014 27th International Conference on VLSI Design, 2014
Co-exploration of NLA kernels and specification of Compute Elements in distributed memory CGRAs.
Proceedings of the XIVth International Conference on Embedded Computer Systems: Architectures, 2014
Proceedings of the XIVth International Conference on Embedded Computer Systems: Architectures, 2014
Energy Efficient, Scalable, and Dynamically Reconfigurable FFT Architecture for OFDM Systems.
Proceedings of the 2014 Fifth International Symposium on Electronic System Design, 2014
2013
High throughput, low latency, memory optimized 64K point FFT architecture using novel radix-4 butterfly unit.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
2011
Data Flow Graph Partitioning Algorithms and Their Evaluations for Optimal Spatio-temporal Computation on a Coarse Grain Reconfigurable Architecture.
IPSJ Trans. Syst. LSI Des. Methodol., 2011
A Method for Flexible Reduction over Binary Fields using a Field Multiplier.
Proceedings of the SECRYPT 2011 - Proceedings of the International Conference on Security and Cryptography, Seville, Spain, 18, 2011
Proceedings of the E-Business and Telecommunications - International Joint Conference, 2011
Dataflow Graph Partitioning for Optimal Spatio-Temporal Computation on a Coarse Grain Reconfigurable Architecture.
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2011
2010
Enhancements for variable N-point streaming FFT/IFFT on REDEFINE, a runtime reconfigurable architecture.
Proceedings of the 2010 International Conference on Embedded Computer Systems: Architectures, 2010
Design space exploration of systolic realization of QR factorization on a runtime reconfigurable platform.
Proceedings of the 2010 International Conference on Embedded Computer Systems: Architectures, 2010
Accelerating Numerical Linear Algebra Kernels on a Scalable Run Time Reconfigurable Platform.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010
Towards minimizing execution delays on dynamically reconfigurable processors: a case study on REDEFINE.
Proceedings of the 2010 International Conference on Compilers, 2010
2009
ACM Trans. Embed. Comput. Syst., 2009
Generic routing rules and a scalable access enhancement for the Network-on-Chip RECONNECT.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009
Proceedings of the 2009 International Conference on Compilers, 2009
Proceedings of the 20th IEEE International Conference on Application-Specific Systems, 2009
Proceedings of the Reconfigurable Computing: Architectures, 2009
2008
Proceedings of the 19th IEEE International Conference on Application-Specific Systems, 2008
Proceedings of the 19th IEEE International Conference on Application-Specific Systems, 2008
Architecture of a polymorphic ASIC for interoperability across multi-mode H.264 decoders.
Proceedings of the 19th IEEE International Conference on Application-Specific Systems, 2008
2007
REDEFINE: Architecture of a SoC Fabric for Runtime Composition of Computation Structures.
Proceedings of the FPL 2007, 2007
2006
Framework for Enabling Highly Available Distributed Applications for Utility Computing.
Proceedings of the Parallel and Distributed Processing and Applications, 2006
2005
Proceedings of the 16th International Workshop on Database and Expert Systems Applications (DEXA 2005), 2005
1993
A Parallel Progressive Refinement Image Rendering Algorithm on a Scalable Multithreaded VLSI Processor Array.
Proceedings of the 1993 International Conference on Parallel Processing, 1993
1990
Microprocessing and Microprogramming, 1990