Saptarsi Das

According to our database, Saptarsi Das authored at least 14 papers between 2009 and 2021.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2021

Transport Triggered near Memory Accelerator for Deep Learning.

Kavitha T. Madhu, Saptarsi Das, Abhishek Tyagi, Ankur Deshwal, Joonho Song, Seungwon Lee

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2020

A Systolic Dataflow Based Accelerator for CNNs.

Saptarsi Das, Arnab Roy, Kiran Kolar Chandrasekharan, Ankur Deshwal, Sehwan Lee

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2017

Energy aware synthesis of application kernels through composition of data-paths on a CGRA.

Nalesh Sivanandan, Kavitha T. Madhu, Saptarsi Das, S. K. Nandy, Ranjani Narayan

Integr., 2017

2016

RHyMe: REDEFINE Hyper Cell Multicore for Accelerating HPC Kernels.

Saptarsi Das, Nalesh Sivanandan, Kavitha T. Madhu, Soumitra Kumar Nandy, Ranjani Narayan

Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

Flexible resource allocation and management for application graphs on ReNÉ MPSoC.

Kavitha T. Madhu, Anuj Rao, Saptarsi Das, Krishna C. Madhava, S. K. Nandy, Ranjani Narayan

Proceedings of the 7th Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures and the 5th Workshop on Design Tools and Architectures For Multicore Embedded Computing Platforms, 2016

2015

Energy Aware Synthesis of Application Kernels Expressed in Functional Languages on a Coarse Grained Composable Reconfigurable Array.

Nalesh Sivanandan, Kavitha T. Madhu, Saptarsi Das, S. K. Nandy, Ranjani Narayan

Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2015

Compiling HPC Kernels for the REDEFINE CGRA.

Kavitha T. Madhu, Saptarsi Das, Nalesh Sivanandan, S. K. Nandy, Ranjani Narayan

Proceedings of the 17th IEEE International Conference on High Performance Computing and Communications, 2015

2014

A framework for post-silicon realization of arbitrary instruction extensions on reconfigurable data-paths.

Saptarsi Das, Kavitha T. Madhu, Madhav Krishna, Nalesh Sivanandan, Farhad Merchant, Santhi Natarajan, Ipsita Biswas, Adithya Pulli, S. K. Nandy, Ranjani Narayan

J. Syst. Archit., 2014

Synthesis of Instruction Extensions on HyperCell, a reconfigurable datapath.

Kavitha T. Madhu, Saptarsi Das, Madhava Krishna C, Nalesh Sivanandan, S. K. Nandy, Ranjani Narayan

Proceedings of the XIVth International Conference on Embedded Computer Systems: Architectures, 2014

2011

Data Flow Graph Partitioning Algorithms and Their Evaluations for Optimal Spatio-temporal Computation on a Coarse Grain Reconfigurable Architecture.

Ratna Krishnamoorthy, Saptarsi Das, Keshavan Varadarajan, Mythri Alle, Masahiro Fujita, Soumitra Kumar Nandy, Ranjani Narayan

IPSJ Trans. Syst. LSI Des. Methodol., 2011

A Method for Flexible Reduction over Binary Fields using a Field Multiplier.

Saptarsi Das, Keshavan Varadarajan, Ganesh Garga, Rajdeep Mondal, Ranjani Narayan, S. K. Nandy

Proceedings of the SECRYPT 2011 - Proceedings of the International Conference on Security and Cryptography, Seville, Spain, 18, 2011

Accelerating Reduction for Enabling Fast Multiplication over Large Binary Fields.

Saptarsi Das, Ranjani Narayan, Soumitra Kumar Nandy

Proceedings of the E-Business and Telecommunications - International Joint Conference, 2011

2009

REDEFINE: Runtime reconfigurable polymorphic ASIC.

Mythri Alle, Keshavan Varadarajan, Alexander Fell, C. Ramesh Reddy, Joseph Nimmy, Saptarsi Das, Prasenjit Biswas, Jugantor Chetia, Adarsha Rao, S. K. Nandy, Ranjani Narayan

ACM Trans. Embed. Comput. Syst., 2009

Streaming FFT on REDEFINE-v2: an application-architecture design space exploration.

Alexander Fell, Mythri Alle, Keshavan Varadarajan, Prasenjit Biswas, Saptarsi Das, Jugantor Chetia, S. K. Nandy, Ranjani Narayan

Proceedings of the 2009 International Conference on Compilers, 2009