Jun Etoh

According to our database, Jun Etoh authored at least 7 papers between 1989 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of three.

2024

Multi-Scale Active Vibration Suppression Technology for Nanometer-Order System.

Jun Etoh, Hironori Ogawa, Hiroki Takahashi

Proceedings of the IEEE/SICE International Symposium on System Integration, 2024

1999

A 29-mm², 1.8-V-only, 16-Mb DINOR flash memory with gate-protected-poly-diode (GPPD) charge pump.

Yoshikazu Miyawaki, Osamu Ishizaki, Yoshihiko Okihara, Tsutomu Inaba, Fumihiko Nitta, Masaaki Mihara, Takashi Hayasaka, Kazuo Kobayashi, Tadashi Omae, Hiroshi Kimura, Satoshi Shimizu, Hiromi Makimoto, Yoshiki Kawajiri, Masashi Wada, Hirofumi Sonoyama, Jun Etoh

IEEE J. Solid State Circuits, 1999

1994

Sub-1-μA dynamic reference voltage generator for battery-operated DRAMs.

Hitoshi Tanaka, Yoshinobu Nakagome, Jun Etoh, Eiji Yamasaki, Masakazu Aoki, Kazuyuki Miyazawa

IEEE J. Solid State Circuits, April, 1994

1991

Dual-regulator dual-decoding-trimmer DRAM voltage limiter for burn-in test.

Masashi Horiguchi, Masakazu Aoki, Jun Etoh, Gyoo Itoh, Kazuhiko Kajigaya, Atsushi Nozoe, Tetsuro Matsumoto

IEEE J. Solid State Circuits, November, 1991

A flexible redundancy technique for high-density DRAMs.

Masashi Horiguchi, Jun Etoh, Masakazu Aoki, Kiyoo Itoh, Tetsuro Matsumoto

IEEE J. Solid State Circuits, January, 1991

1990

A tunable CMOS-DRAM voltage limiter with stabilized feedback amplifier.

Masashi Horiguchi, Masakazu Aoki, Jun Etoh, Hitoshi Tanaka, Shin'ichi Ikenaga, Kiyoo Itoh, Kazuhiko Kajigaya, Hiroaki Kotani, Kazuyoshi Ohshima, Tetsuro Matsumoto

IEEE J. Solid State Circuits, October, 1990

1989

A 1.5-V DRAM for battery-based applications.

Masakazu Aoki, Jun Etoh, Kiyoo Itoh, Shin Kimura, Yoshifumi Kawamoto

IEEE J. Solid State Circuits, October, 1989