Kiyoung Choi

According to our database1, Kiyoung Choi authored at least 189 papers between 1988 and 2019.

Collaborative distances:

Awards

IEEE Fellow

IEEE Fellow 2017, "For contribution to low-power, real-time, and reconfigurable systems".

Timeline

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Links

On csauthors.net:

Bibliography

2019
Autoencoder-Based Incremental Class Learning without Retraining on Old Data.
CoRR, 2019

VCAM: Variation Compensation through Activation Matching for Analog Binarized Neural Networks.
Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019

Aging Gracefully with Approximation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Acceleration of DNN Backward Propagation by Selective Computation of Gradients.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Cell division: weight bit-width reduction technique for convolutional neural network hardware accelerators.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

Network Recasting: A Universal Method for Network Architecture Transformation.
Proceedings of the Thirty-Third AAAI Conference on Artificial Intelligence, 2019

2018
Delay Monitoring System With Multiple Generic Monitors for Wide Voltage Range Operation.
IEEE Trans. VLSI Syst., 2018

An Efficient and Accurate Stochastic Number Generator Using Even-Distribution Coding.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

Benzene: An Energy-Efficient Distributed Hybrid Cache Architecture for Manycore Systems.
TACO, 2018

Deep neural networks with weighted spikes.
Neurocomputing, 2018

Reconfigurable Multi-Input Adder Design for Deep Neural Network Accelerators.
Proceedings of the International SoC Design Conference, 2018

Energy Efficient Analog Synapse/Neuron Circuit for Binarized Neural Networks.
Proceedings of the International SoC Design Conference, 2018

Tapered-Ratio Compression for Residual Network.
Proceedings of the International SoC Design Conference, 2018

ComPEND: Computation Pruning through Early Negative Detection for ReLU in a Deep Neural Network Accelerator.
Proceedings of the 32nd International Conference on Supercomputing, 2018

Training Neural Networks with Low Precision Dynamic Fixed-Point.
Proceedings of the 36th IEEE International Conference on Computer Design, 2018

Architectures and algorithms for user customization of CNNs.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

Speaker Verification based on Deep Neural Network for Text-Constrained Short Commands.
Proceedings of the Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, 2018

2017
Reconfigurable Architectures.
Proceedings of the Handbook of Hardware/Software Codesign., 2017

Excavating the Hidden Parallelism Inside DRAM Architectures With Buffered Compares.
IEEE Trans. VLSI Syst., 2017

Dirty-Block Tracking in a Direct-Mapped DRAM Cache with Self-Balancing Dispatch.
TACO, 2017

ExtraV: Boosting Graph Processing Near Storage with a Coherent Accelerator.
PVLDB, 2017

Autonomic Diffusive Load Balancing on Many-Core Architecture Using Simulated Annealing.
IEICE Transactions, 2017

Optimal mapping of program overlays onto many-core platforms with limited memory capacity.
Design Autom. for Emb. Sys., 2017

Synthesis of multi-variate stochastic computing circuits.
Proceedings of the 2017 IFIP/IEEE International Conference on Very Large Scale Integration, 2017

Hybrid spiking-stochastic Deep Neural Network.
Proceedings of the 2017 International Symposium on VLSI Design, Automation and Test, 2017

A new stochastic mutiplier for deep neural networks.
Proceedings of the International SoC Design Conference, 2017

Accurate and Efficient Stochastic Computing Hardware for Convolutional Neural Networks.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

FPGA implementation of convolutional neural network based on stochastic computing.
Proceedings of the International Conference on Field Programmable Technology, 2017

Design space exploration of FPGA accelerators for convolutional neural networks.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

A space- and energy-efficient code Compression/Decompression technique for coarse-grained reconfigurable architectures.
Proceedings of the 2017 International Symposium on Code Generation and Optimization, 2017

Incremental training of CNNs for user customization: work-in-progress.
Proceedings of the 2017 International Conference on Compilers, 2017

Scalable stochastic-computing accelerator for convolutional neural networks.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016
Low-Power Hybrid Memory Cubes With Link Power Management and Two-Level Prefetching.
IEEE Trans. VLSI Syst., 2016

Prediction Hybrid Cache: An Energy-Efficient STT-RAM Cache Architecture.
IEEE Trans. Computers, 2016

AIM: Energy-Efficient Aggregation Inside the Memory Hierarchy.
TACO, 2016

A design framework for hierarchical ensemble of multiple feature extractors and multiple classifiers.
Pattern Recognition, 2016

Exploration of trade-offs in the design of volatile STT-RAM cache.
Journal of Systems Architecture - Embedded Systems Design, 2016

Adaptively weighted round-robin arbitration for equality of service in a many-core network-on-chip.
IET Computers & Digital Techniques, 2016

Dynamic clock synchronization scheme between voltage domains in multi-core architecture.
Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016

A new approach to binarizing neural networks.
Proceedings of the International SoC Design Conference, 2016

Efficient FPGA acceleration of Convolutional Neural Networks using logical-3D compute array.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Buffered compares: Excavating the hidden parallelism inside DRAM architectures with lightweight logic.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Adaptive delay monitoring for wide voltage-range operation.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Dynamic energy-accuracy trade-off using stochastic computing in deep neural networks.
Proceedings of the 53rd Annual Design Automation Conference, 2016

An energy-efficient random number generator for stochastic circuits.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015
Guest Editorial for Special Issue on Emerging Memory Technologies - Modeling, Design, and Applications for Multi-Scale Computing.
IEEE Trans. Multi-Scale Computing Systems, 2015

REDELF: An Energy-Efficient Deadlock-Free Routing for 3D NoCs with Partial Vertical Connections.
JETC, 2015

Dynamic error tracking and supply voltage adjustment for low power.
Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015

Energy-efficient exclusive last-level hybrid caches consisting of SRAM and STT-RAM.
Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015

Message from the general chairs.
Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015

PIM-enabled instructions: a low-overhead, locality-aware processing-in-memory architecture.
Proceedings of the 42nd Annual International Symposium on Computer Architecture, 2015

A scalable processing-in-memory accelerator for parallel graph processing.
Proceedings of the 42nd Annual International Symposium on Computer Architecture, 2015

THOR: Orchestrated thermal management of cores and networks in 3D many-core architectures.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014
LASIC: Loop-Aware Sleepy Instruction Caches Based on STT-RAM Technology.
IEEE Trans. VLSI Syst., 2014

Introduction to the Special Issue on the 11th International Conference on Field-Programmable Technology (FPT'12).
TRETS, 2014

Configurable range memory for effective data reuse on programmable accelerators.
ACM Trans. Design Autom. Electr. Syst., 2014

Critical-path-aware high-level synthesis with distributed controller for fast timing closure.
ACM Trans. Design Autom. Electr. Syst., 2014

Software-Level Approaches for Tolerating Transient Faults in a Coarse-GrainedReconfigurable Architecture.
IEEE Trans. Dependable Sec. Comput., 2014

Design of a coarse-grained reconfigurable architecture with floating-point support and comparative study.
Integration, 2014

Energy-efficient partitioning of hybrid caches in multi-core architecture.
Proceedings of the 22nd International Conference on Very Large Scale Integration, 2014

An FPGA implementation of high-throughput key-value store using Bloom filter.
Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014

Tree-Mesh Heterogeneous Topology for Low-Latency NoC.
Proceedings of the 2014 International Workshop on Network on Chip Architectures, 2014

Concept-aware ensemble system for pedestrian detection.
Proceedings of the 2014 IEEE Intelligent Vehicles Symposium Proceedings, 2014

DASCA: Dead Write Prediction Assisted STT-RAM Cache Architecture.
Proceedings of the 20th IEEE International Symposium on High Performance Computer Architecture, 2014

Dynamic Power Management of Off-Chip Links for Hybrid Memory Cubes.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Leveraging parallelism in the presence of control flow on CGRAs.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013
Deflection routing in 3D network-on-chip with limited vertical bandwidth.
ACM Trans. Design Autom. Electr. Syst., 2013

Mapping and Scheduling of Tasks and Communications on Many-Core SoC Under Local Memory Constraint.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2013

Isomorphism-Aware Identification of Custom Instructions With I/O Serialization.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2013

Power-Efficient Predication Techniques for Acceleration of Control Flow Execution on CGRA.
TACO, 2013

CPU-based speed acceleration techniques for shear warp volume rendering.
Multimedia Tools Appl., 2013

A deadlock-free routing algorithm requiring no virtual channel on 3D-NoCs with partial vertical connections.
Proceedings of the 2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2013

Enhancing Utilization of Integer Functional Units for High-Throughput Floating Point Operations on Coarse-Grained Reconfigurable Architecture.
Proceedings of the Multimedia and Ubiquitous Engineering, 2013

Towards optimal adaptive routing in 3D NoC with limited vertical bandwidth.
Proceedings of the Network on Chip Architectures, 2013

Write intensity prediction for energy-efficient non-volatile caches.
Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013

Compiling control-intensive loops for CGRAs with state-based full predication.
Proceedings of the Design, Automation and Test in Europe, 2013

Deflection routing in 3D Network-on-Chip with TSV serialization.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

Selectively protecting error-correcting code for area-efficient and reliable STT-RAM caches.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012
Active Memory Processor for Network-on-Chip-Based Architecture.
IEEE Trans. Computers, 2012

ESL Design Methodology.
J. Electrical and Computer Engineering, 2012

Exploiting New Interconnect Technologies in On-Chip Communication.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2012

Guest Editorial New Interconnect Technologies in On-Chip Communication.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2012

An adaptive routing algorithm for 3D mesh NoC with limited vertical bandwidth.
Proceedings of the 20th IEEE/IFIP International Conference on VLSI and System-on-Chip, 2012

Position-based weighted round-robin arbitration for equality of service in many-core network-on-chips.
Proceedings of the Fifth International Workshop on Network on Chip Architectures, 2012

Resource-shared custom instruction generation under performance/area constraints.
Proceedings of the 2012 International Symposium on System on Chip, 2012

A Memetic Quantum-Inspired Evolutionary Algorithm for circuit bipartitioning problem.
Proceedings of the International SoC Design Conference, 2012

Lower-bits cache for low power STT-RAM caches.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

State-based full predication for low power coarse-grained reconfigurable architecture.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Memory-aware mapping and scheduling of tasks and communications on many-core SoC.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011
Mapping Multi-Domain Applications Onto Coarse-Grained Reconfigurable Architectures.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2011

Coarse-Grained Reconfigurable Array: Architecture and Application Mapping.
IPSJ Trans. System LSI Design Methodology, 2011

Resonant properties of piezoelectric cantilever transducers fabricated on the SiC membrane.
Proceedings of the 6th IEEE International Conference on Nano/Micro Engineered and Molecular Systems, 2011

3D network-on-chip with wireless links through inductive coupling.
Proceedings of the International SoC Design Conference, 2011

A host-accelerator communication architecture design for efficient binary acceleration.
Proceedings of the International SoC Design Conference, 2011

CRM: Configurable Range Memory for Fast Reconfigurable Computing.
Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011

High-level synthesis with distributed controller for fast timing closure.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

Simulated annealing-based diffusive load balancing on many-core SoC.
Proceedings of the 8th International Conference on Autonomic Computing, 2011

An efficient algorithm for isomorphism-aware custom instruction identification for extensible processors.
Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis, 2011

A polynomial-time custom instruction identification algorithm based on dynamic programming.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010
Design Space Exploration for Efficient Resource Utilization in Coarse-Grained Reconfigurable Architecture.
IEEE Trans. VLSI Syst., 2010

Binary acceleration using coarse-grained reconfigurable architecture.
SIGARCH Computer Architecture News, 2010

Communication architecture design for reconfigurable multimedia SoC platform.
Design Autom. for Emb. Sys., 2010

Automatic mapping of control-intensive kernels onto coarse-grained reconfigurable array architecture with speculative execution.
Proceedings of the 24th IEEE International Symposium on Parallel and Distributed Processing, 2010

Acceleration of control flow on CGRA using advanced predicated execution.
Proceedings of the International Conference on Field-Programmable Technology, 2010

Routing-Aware Application Mapping Considering Steiner Points for Coarse-Grained Reconfigurable Architecture.
Proceedings of the Reconfigurable Computing: Architectures, 2010

Memory-Centric Communication Architecture for Reconfigurable Computing.
Proceedings of the Reconfigurable Computing: Architectures, 2010

Thermal-aware fault-tolerant system design with coarse-grained reconfigurable array architecture.
Proceedings of the 2010 NASA/ESA Conference on Adaptive Hardware and Systems, 2010

2009
Topology/Floorplan/Pipeline Co-Design of Cascaded Crossbar Bus.
IEEE Trans. VLSI Syst., 2009

Low Power Reconfiguration Technique for Coarse-Grained Reconfigurable Architecture.
IEEE Trans. VLSI Syst., 2009

Coarse-grained reconfigurable architecture for multiple application domains: a case study.
Proceedings of the 2009 International Conference on Hybrid Information Technology, 2009

Multiprocessor System-on-Chip designs with active memory processors for higher memory efficiency.
Proceedings of the 46th Design Automation Conference, 2009

Code decomposition and recomposition for enhancing embedded software performance.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008
SoCDAL: System-on-chip design AcceLerator.
ACM Trans. Design Autom. Electr. Syst., 2008

Introduction to embedded systems week 2006 special issue.
ACM Trans. Embedded Comput. Syst., 2008

Evaluating memory architectures for media applications on Coarse-grained Reconfigurable Architectures.
IJES, 2008

A Generic Design for Encoding and Decoding Variable Length Codes in Multi-codec Video Processing Engines.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008

Entry control in network-on-chip for memory power reduction.
Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008

2007
Instruction set synthesis with efficient instruction encoding for configurable processors.
ACM Trans. Design Autom. Electr. Syst., 2007

Fast cycle-approximate MPSoC simulation based on synchronization time-point prediction.
Design Autom. for Emb. Sys., 2007

Scheduling with accurate communication delay model and scheduler implementation for multiprocessor system-on-chip.
Design Autom. for Emb. Sys., 2007

Implementation of floating-point operations for 3D graphics on a coarse-grained reconfigurable architecture.
Proceedings of the 2007 IEEE International SOC Conference, 2007

Automatic Bus Matrix Synthesis based on Hardware Interface Selection for Fast Communication Design Space Exploration.
Proceedings of the 2007 International Conference on Embedded Computer Systems: Architectures, 2007

Buffer Size Reduction through Control-Flow Decomposition.
Proceedings of the 13th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2007), 2007

Low Runtime-Overhead Software Synthesis for Communicating Concurrent Processes.
Proceedings of the 18th IEEE International Workshop on Rapid System Prototyping (RSP 2007), 2007

Communication Architecture Synthesis of Cascaded Bus Matrix.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

Memory Operation Inclusive Instruction-Set Extensions and Data Path Generation.
Proceedings of the IEEE International Conference on Application-Specific Systems, 2007

2006
Power-conscious configuration cache structure and code mapping for coarse-grained reconfigurable architecture.
Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006

A spatial mapping algorithm for heterogeneous coarse-grained reconfigurable architectures.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Worst case execution time analysis for synthesized hardware.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005
Pipelining with common operands for power-efficient linear systems.
IEEE Trans. VLSI Syst., 2005

Resource Sharing and Pipelining in Coarse-Grained Reconfigurable Architecture for Domain-Specific Optimization.
Proceedings of the 2005 Design, 2005

Scheduler implementation in MP SoC design.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
Application-specific configuration of multithreaded processor architecture for embedded applications.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

A Mobility Analysis Method of Closed-chain Mechanisms with Over-constraints and Non-holonomic Constraints.
Proceedings of the 2004 IEEE International Conference on Robotics and Automation, 2004

Memory and architecture exploration with thread shifting for multithreaded processors in embedded systems.
Proceedings of the 2004 International Conference on Compilers, 2004

2003
Compilation Approach for Coarse-Grained Reconfigurable Architectures.
IEEE Design & Test of Computers, 2003

An Efficient Simulation Environment and Simulation Techniques for Bluetooth Device Design.
Design Autom. for Emb. Sys., 2003

Configurable Processors for Embedded Computing.
IEEE Computer, 2003

An algorithm for mapping loops onto coarse-grained reconfigurable architectures.
Proceedings of the 2003 Conference on Languages, 2003

Energy-efficient instruction set synthesis for application-specific processors.
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

Scheduling and Timing Analysis of HW/SW On-Chip Communication in MP SoC Design.
Proceedings of the 2003 Design, 2003

Evaluating Memory Architectures for Media Applications on Coarse-Grained Recon.gurable Architectures.
Proceedings of the 14th IEEE International Conference on Application-Specific Systems, 2003

Scheduling and Timing Analysis of HW/SW On-Chip Communication in MP SoC Design.
Proceedings of the Embedded Software for SoC, 2003

2002
An intra-task dynamic voltage scaling method for SoC design with hierarchical FSM and synchronous dataflow model.
Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002

Efficient instruction encoding for automatic instruction set design of configurable ASIPs.
Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

Reconfigurable SoC design with hierarchical FSM and synchronous dataflow model.
Proceedings of the Tenth International Symposium on Hardware/Software Codesign, 2002

2001
Power-conscious Scheduling for Real-time Embedded Systems Design.
VLSI Design, 2001

Narrow bus encoding for low-power DSP systems.
IEEE Trans. VLSI Syst., 2001

Partial bus-invert coding for power optimization of application-specific systems.
IEEE Trans. VLSI Syst., 2001

Performance-driven high-level synthesis with bit-level chaining andclock selection.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2001

Low power pipelining of linear systems: a common operand centric approach.
Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001

Behavior-to-Placed RTL Synthesis with Performance-Driven Placement.
Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

Performance improvement of multi-processor systems cosimulation based on SW analysis.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

Area-efficient buffer binding based on a novel two-port FIFO structure.
Proceedings of the Ninth International Symposium on Hardware/Software Codesign, 2001

Scheduling-based code size reduction in processors with indirect addressing mode.
Proceedings of the Ninth International Symposium on Hardware/Software Codesign, 2001

High-level synthesis under multi-cycle interconnect delay.
Proceedings of ASP-DAC 2001, 2001

2000
Performance improvement of geographically distributed cosimulation by hierarchically grouped messages.
IEEE Trans. VLSI Syst., 2000

Optimizing Timed Cosimulation by Hybrid Synchronization.
Design Autom. for Emb. Sys., 2000

Low power self-timed Radix-2 division (poster session).
Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000

Power minimization of functional units partially guarded computation.
Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000

A new cost model for high-level power optimization and its application.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

Power Optimization of Real-Time Embedded Systems on Variable Speed Processors.
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

Fast Hardware-Software Coverification by Optimistic Execution of Real Processor.
Proceedings of the 2000 Design, 2000

Schedulability-driven performance analysis of multiple mode embedded real-time systems.
Proceedings of the 37th Conference on Design Automation, 2000

Performance estimation of multiple-cache IP-based systems: case study of an interdependency problem and application of an extended shared memory model.
Proceedings of the Eighth International Workshop on Hardware/Software Codesign, 2000

Narrow bus encoding for low power systems.
Proceedings of ASP-DAC 2000, 2000

Hardware-software cosynthesis for run-time incrementally reconfigurable FPGAs.
Proceedings of ASP-DAC 2000, 2000

1999
Exploiting Early Partial Reconfiguration of Run-Time Reconfigurable FPGAs in Embedded Systems Design.
Proceedings of the 1999 ACM/SIGDA Seventh International Symposium on Field Programmable Gate Arrays, 1999

Power Conscious Fixed Priority Scheduling for Hard Real-Time Systems.
Proceedings of the 36th Conference on Design Automation, 1999

Performance-Driven Scheduling with Bit-Level Chaining.
Proceedings of the 36th Conference on Design Automation, 1999

Optimizing geographically distributed timed cosimulation by hierarchically grouped messages.
Proceedings of the Seventh International Workshop on Hardware/Software Codesign, 1999

1998
An Integrated Cosimulation Environment for Heterogeneous Systems Prototyping.
Design Autom. for Emb. Sys., 1998

Partial bus-invert coding for power optimization of system level bus.
Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998

Rate Assignment for Embedded Reactive Real-Time Systems.
Proceedings of the 24th EUROMICRO '98 Conference, 1998

Optimistic distributed timed cosimulation based on thread simulation model.
Proceedings of the Sixth International Workshop on Hardware/Software Codesign, 1998

Loop Pipelining in Hardware-Software Partitioning.
Proceedings of the ASP-DAC '98, 1998

1997
Low power high level synthesis by increasing data correlation.
Proceedings of the 1997 International Symposium on Low Power Electronics and Design, 1997

Power-conscious High Level Synthesis Using Loop Folding.
Proceedings of the 34st Conference on Design Automation, 1997

Enforcing Schedulability of Multi-Task Systems by Hardware-Software Codesign.
Proceedings of the Fifth International Workshop on Hardware/Software Codesign, 1997

1996
Self-timed divider based on RSD number system.
IEEE Trans. VLSI Syst., 1996

Hardware-Software Codesign of Resource-Constrained Real-Time Systems.
Proceedings of the Third International Workshop on Real-Time Computing Systems Application (RTCSA '96), October 30, 1996

An integrated hardware-software cosimulation environment with automated interface generation.
Proceedings of the Seventh IEEE International Workshop on Rapid System Prototyping (RSP '96), 1996

Software synthesis through task decomposition by dependency analysis.
Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996

Thread-based software synthesis for embedded system design.
Proceedings of the 1996 European Design and Test Conference, 1996

1995
Efficient Prototyping System Based on Incremental Design and Module-by-Module Verification.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

An integrated hardware-software cosimulation environment for heterogeneous systems prototyping.
Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29, 1995

1994
A Self-Timed Divider Using RSD Number System.
Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994

1988
Fast functional simulation: an incremental approach.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1988

Incremental-in-time Algorithm for Digital Simulation.
Proceedings of the 25th ACM/IEEE Conference on Design Automation, 1988


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