Kiyoung Choi
Orcid: 0000-0001-6138-6697
According to our database1,
Kiyoung Choi
authored at least 196 papers
between 1988 and 2023.
Collaborative distances:
Collaborative distances:
Awards
IEEE Fellow
IEEE Fellow 2017, "For contribution to low-power, real-time, and reconfigurable systems".
Timeline
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On csauthors.net:
Bibliography
2023
Retrospective: A Scalable Processing-in-Memory Accelerator for Parallel Graph Processing.
CoRR, 2023
Proceedings of the IEEE/ASME International Conference on Advanced Intelligent Mechatronics, 2023
2022
ComPreEND: Computation Pruning through Predictive Early Negative Detection for ReLU in a Deep Neural Network Accelerator.
IEEE Trans. Computers, 2022
Human-Robot Interaction Force based Power Assistive Algorithm of Upper Limb Exoskeleton Robots Driven by a Series Elastic Actuator.
Proceedings of the IECON 2022, 2022
2021
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2021
2020
IEEE Trans. Circuits Syst. I Fundam. Theory Appl., 2020
2019
CoRR, 2019
Proceedings of the 2019 International SoC Design Conference, 2019
VCAM: Variation Compensation through Activation Matching for Analog Binarized Neural Networks.
Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
Cell division: weight bit-width reduction technique for convolutional neural network hardware accelerators.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019
Proceedings of the Thirty-Third AAAI Conference on Artificial Intelligence, 2019
2018
Delay Monitoring System With Multiple Generic Monitors for Wide Voltage Range Operation.
IEEE Trans. Very Large Scale Integr. Syst., 2018
An Efficient and Accurate Stochastic Number Generator Using Even-Distribution Coding.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
Benzene: An Energy-Efficient Distributed Hybrid Cache Architecture for Manycore Systems.
ACM Trans. Archit. Code Optim., 2018
Proceedings of the International SoC Design Conference, 2018
Proceedings of the International SoC Design Conference, 2018
Proceedings of the International SoC Design Conference, 2018
ComPEND: Computation Pruning through Early Negative Detection for ReLU in a Deep Neural Network Accelerator.
Proceedings of the 32nd International Conference on Supercomputing, 2018
Proceedings of the 36th IEEE International Conference on Computer Design, 2018
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018
Speaker Verification based on Deep Neural Network for Text-Constrained Short Commands.
Proceedings of the Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, 2018
2017
Proceedings of the Handbook of Hardware/Software Codesign., 2017
IEEE Trans. Very Large Scale Integr. Syst., 2017
ACM Trans. Archit. Code Optim., 2017
Proc. VLDB Endow., 2017
Autonomic Diffusive Load Balancing on Many-Core Architecture Using Simulated Annealing.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017
Optimal mapping of program overlays onto many-core platforms with limited memory capacity.
Des. Autom. Embed. Syst., 2017
Proceedings of the 2017 IFIP/IEEE International Conference on Very Large Scale Integration, 2017
Proceedings of the 2017 International Symposium on VLSI Design, Automation and Test, 2017
Proceedings of the International SoC Design Conference, 2017
Accurate and Efficient Stochastic Computing Hardware for Convolutional Neural Networks.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017
Proceedings of the International Conference on Field Programmable Technology, 2017
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
A space- and energy-efficient code Compression/Decompression technique for coarse-grained reconfigurable architectures.
Proceedings of the 2017 International Symposium on Code Generation and Optimization, 2017
Proceedings of the 2017 International Conference on Compilers, 2017
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017
2016
IEEE Trans. Very Large Scale Integr. Syst., 2016
IEEE Trans. Computers, 2016
ACM Trans. Archit. Code Optim., 2016
A design framework for hierarchical ensemble of multiple feature extractors and multiple classifiers.
Pattern Recognit., 2016
J. Syst. Archit., 2016
Adaptively weighted round-robin arbitration for equality of service in a many-core network-on-chip.
IET Comput. Digit. Tech., 2016
Dynamic clock synchronization scheme between voltage domains in multi-core architecture.
Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016
Proceedings of the International SoC Design Conference, 2016
Efficient FPGA acceleration of Convolutional Neural Networks using logical-3D compute array.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
Buffered compares: Excavating the hidden parallelism inside DRAM architectures with lightweight logic.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
Dynamic energy-accuracy trade-off using stochastic computing in deep neural networks.
Proceedings of the 53rd Annual Design Automation Conference, 2016
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016
2015
Guest Editorial for Special Issue on Emerging Memory Technologies - Modeling, Design, and Applications for Multi-Scale Computing.
IEEE Trans. Multi Scale Comput. Syst., 2015
REDELF: An Energy-Efficient Deadlock-Free Routing for 3D NoCs with Partial Vertical Connections.
ACM J. Emerg. Technol. Comput. Syst., 2015
Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015
Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015
Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015
PIM-enabled instructions: a low-overhead, locality-aware processing-in-memory architecture.
Proceedings of the 42nd Annual International Symposium on Computer Architecture, 2015
Proceedings of the 42nd Annual International Symposium on Computer Architecture, 2015
THOR: Orchestrated thermal management of cores and networks in 3D many-core architectures.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015
2014
IEEE Trans. Very Large Scale Integr. Syst., 2014
Introduction to the Special Issue on the 11<sup>th</sup> International Conference on Field-Programmable Technology (FPT'12).
ACM Trans. Reconfigurable Technol. Syst., 2014
ACM Trans. Design Autom. Electr. Syst., 2014
Critical-path-aware high-level synthesis with distributed controller for fast timing closure.
ACM Trans. Design Autom. Electr. Syst., 2014
Software-Level Approaches for Tolerating Transient Faults in a Coarse-GrainedReconfigurable Architecture.
IEEE Trans. Dependable Secur. Comput., 2014
Design of a coarse-grained reconfigurable architecture with floating-point support and comparative study.
Integr., 2014
Proceedings of the 22nd International Conference on Very Large Scale Integration, 2014
Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014
Proceedings of the 2014 International Workshop on Network on Chip Architectures, 2014
Proceedings of the 2014 IEEE Intelligent Vehicles Symposium Proceedings, 2014
Proceedings of the 20th IEEE International Symposium on High Performance Computer Architecture, 2014
Proceedings of the 51st Annual Design Automation Conference 2014, 2014
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014
2013
ACM Trans. Design Autom. Electr. Syst., 2013
Mapping and Scheduling of Tasks and Communications on Many-Core SoC Under Local Memory Constraint.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013
Power-Efficient Predication Techniques for Acceleration of Control Flow Execution on CGRA.
ACM Trans. Archit. Code Optim., 2013
Multim. Tools Appl., 2013
A deadlock-free routing algorithm requiring no virtual channel on 3D-NoCs with partial vertical connections.
Proceedings of the 2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2013
Enhancing Utilization of Integer Functional Units for High-Throughput Floating Point Operations on Coarse-Grained Reconfigurable Architecture.
Proceedings of the Multimedia and Ubiquitous Engineering, 2013
Proceedings of the Network on Chip Architectures, 2013
Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013
Proceedings of the Design, Automation and Test in Europe, 2013
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013
Selectively protecting error-correcting code for area-efficient and reliable STT-RAM caches.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013
2012
IEEE Trans. Computers, 2012
IEEE J. Emerg. Sel. Topics Circuits Syst., 2012
IEEE J. Emerg. Sel. Topics Circuits Syst., 2012
Proceedings of the 20th IEEE/IFIP International Conference on VLSI and System-on-Chip, 2012
Position-based weighted round-robin arbitration for equality of service in many-core network-on-chips.
Proceedings of the Fifth International Workshop on Network on Chip Architectures, 2012
Proceedings of the 2012 International Symposium on System on Chip, 2012
A Memetic Quantum-Inspired Evolutionary Algorithm for circuit bipartitioning problem.
Proceedings of the International SoC Design Conference, 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
State-based full predication for low power coarse-grained reconfigurable architecture.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012
2011
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011
IPSJ Trans. Syst. LSI Des. Methodol., 2011
Resonant properties of piezoelectric cantilever transducers fabricated on the SiC membrane.
Proceedings of the 6th IEEE International Conference on Nano/Micro Engineered and Molecular Systems, 2011
Proceedings of the International SoC Design Conference, 2011
A host-accelerator communication architecture design for efficient binary acceleration.
Proceedings of the International SoC Design Conference, 2011
Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011
Proceedings of the 8th International Conference on Autonomic Computing, 2011
An efficient algorithm for isomorphism-aware custom instruction identification for extensible processors.
Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis, 2011
A polynomial-time custom instruction identification algorithm based on dynamic programming.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011
2010
Design Space Exploration for Efficient Resource Utilization in Coarse-Grained Reconfigurable Architecture.
IEEE Trans. Very Large Scale Integr. Syst., 2010
SIGARCH Comput. Archit. News, 2010
Des. Autom. Embed. Syst., 2010
Automatic mapping of control-intensive kernels onto coarse-grained reconfigurable array architecture with speculative execution.
Proceedings of the 24th IEEE International Symposium on Parallel and Distributed Processing, 2010
Proceedings of the International Conference on Field-Programmable Technology, 2010
Routing-Aware Application Mapping Considering Steiner Points for Coarse-Grained Reconfigurable Architecture.
Proceedings of the Reconfigurable Computing: Architectures, 2010
Proceedings of the Reconfigurable Computing: Architectures, 2010
Thermal-aware fault-tolerant system design with coarse-grained reconfigurable array architecture.
Proceedings of the 2010 NASA/ESA Conference on Adaptive Hardware and Systems, 2010
2009
IEEE Trans. Very Large Scale Integr. Syst., 2009
IEEE Trans. Very Large Scale Integr. Syst., 2009
Coarse-grained reconfigurable architecture for multiple application domains: a case study.
Proceedings of the 2009 International Conference on Hybrid Information Technology, 2009
Multiprocessor System-on-Chip designs with active memory processors for higher memory efficiency.
Proceedings of the 46th Design Automation Conference, 2009
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009
2008
ACM Trans. Design Autom. Electr. Syst., 2008
ACM Trans. Embed. Comput. Syst., 2008
Evaluating memory architectures for media applications on Coarse-grained Reconfigurable Architectures.
Int. J. Embed. Syst., 2008
A Generic Design for Encoding and Decoding Variable Length Codes in Multi-codec Video Processing Engines.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008
Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008
2007
Instruction set synthesis with efficient instruction encoding for configurable processors.
ACM Trans. Design Autom. Electr. Syst., 2007
Fast cycle-approximate MPSoC simulation based on synchronization time-point prediction.
Des. Autom. Embed. Syst., 2007
Scheduling with accurate communication delay model and scheduler implementation for multiprocessor system-on-chip.
Des. Autom. Embed. Syst., 2007
Implementation of floating-point operations for 3D graphics on a coarse-grained reconfigurable architecture.
Proceedings of the 2007 IEEE International SOC Conference, 2007
Automatic Bus Matrix Synthesis based on Hardware Interface Selection for Fast Communication Design Space Exploration.
Proceedings of the 2007 International Conference on Embedded Computer Systems: Architectures, 2007
Proceedings of the 13th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2007), 2007
Proceedings of the 18th IEEE International Workshop on Rapid System Prototyping (RSP 2007), 2007
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007
Proceedings of the IEEE International Conference on Application-Specific Systems, 2007
2006
Power-conscious configuration cache structure and code mapping for coarse-grained reconfigurable architecture.
Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006
A spatial mapping algorithm for heterogeneous coarse-grained reconfigurable architectures.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006
2005
IEEE Trans. Very Large Scale Integr. Syst., 2005
Resource Sharing and Pipelining in Coarse-Grained Reconfigurable Architecture for Domain-Specific Optimization.
Proceedings of the 2005 Design, 2005
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005
2004
Application-specific configuration of multithreaded processor architecture for embedded applications.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
A Mobility Analysis Method of Closed-chain Mechanisms with Over-constraints and Non-holonomic Constraints.
Proceedings of the 2004 IEEE International Conference on Robotics and Automation, 2004
Memory and architecture exploration with thread shifting for multithreaded processors in embedded systems.
Proceedings of the 2004 International Conference on Compilers, 2004
2003
IEEE Des. Test Comput., 2003
An Efficient Simulation Environment and Simulation Techniques for Bluetooth Device Design.
Des. Autom. Embed. Syst., 2003
Proceedings of the 2003 Conference on Languages, 2003
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003
Proceedings of the 2003 Design, 2003
Evaluating Memory Architectures for Media Applications on Coarse-Grained Recon.gurable Architectures.
Proceedings of the 14th IEEE International Conference on Application-Specific Systems, 2003
Proceedings of the Embedded Software for SoC, 2003
2002
An intra-task dynamic voltage scaling method for SoC design with hierarchical FSM and synchronous dataflow model.
Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002
Efficient instruction encoding for automatic instruction set design of configurable ASIPs.
Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002
Proceedings of the Tenth International Symposium on Hardware/Software Codesign, 2002
2001
IEEE Trans. Very Large Scale Integr. Syst., 2001
IEEE Trans. Very Large Scale Integr. Syst., 2001
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001
Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001
Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001
Performance improvement of multi-processor systems cosimulation based on SW analysis.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001
Proceedings of the Ninth International Symposium on Hardware/Software Codesign, 2001
Proceedings of the Ninth International Symposium on Hardware/Software Codesign, 2001
Proceedings of ASP-DAC 2001, 2001
2000
Performance improvement of geographically distributed cosimulation by hierarchically grouped messages.
IEEE Trans. Very Large Scale Integr. Syst., 2000
Des. Autom. Embed. Syst., 2000
Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000
Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000
Proceedings of the 2000 Design, 2000
Schedulability-driven performance analysis of multiple mode embedded real-time systems.
Proceedings of the 37th Conference on Design Automation, 2000
Performance estimation of multiple-cache IP-based systems: case study of an interdependency problem and application of an extended shared memory model.
Proceedings of the Eighth International Workshop on Hardware/Software Codesign, 2000
Proceedings of ASP-DAC 2000, 2000
1999
Exploiting Early Partial Reconfiguration of Run-Time Reconfigurable FPGAs in Embedded Systems Design.
Proceedings of the 1999 ACM/SIGDA Seventh International Symposium on Field Programmable Gate Arrays, 1999
Proceedings of the 36th Conference on Design Automation, 1999
Proceedings of the 36th Conference on Design Automation, 1999
Optimizing geographically distributed timed cosimulation by hierarchically grouped messages.
Proceedings of the Seventh International Workshop on Hardware/Software Codesign, 1999
1998
Des. Autom. Embed. Syst., 1998
Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998
Proceedings of the 24th EUROMICRO '98 Conference, 1998
Proceedings of the Sixth International Workshop on Hardware/Software Codesign, 1998
Proceedings of the ASP-DAC '98, 1998
1997
Proceedings of the 1997 International Symposium on Low Power Electronics and Design, 1997
Proceedings of the 34st Conference on Design Automation, 1997
Proceedings of the Fifth International Workshop on Hardware/Software Codesign, 1997
1996
IEEE Trans. Very Large Scale Integr. Syst., 1996
Proceedings of the Third International Workshop on Real-Time Computing Systems Application (RTCSA '96), October 30, 1996
An integrated hardware-software cosimulation environment with automated interface generation.
Proceedings of the Seventh IEEE International Workshop on Rapid System Prototyping (RSP '96), 1996
Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996
Proceedings of the 1996 European Design and Test Conference, 1996
1995
Efficient Prototyping System Based on Incremental Design and Module-by-Module Verification.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995
An integrated hardware-software cosimulation environment for heterogeneous systems prototyping.
Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29, 1995
1994
Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994
1988
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988
Proceedings of the 25th ACM/IEEE Conference on Design Automation, 1988