Junwhan Ahn

According to our database, Junwhan Ahn authored at least 34 papers between 2011 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

Retrospective: A Scalable Processing-in-Memory Accelerator for Parallel Graph Processing.

Junwhan Ahn, Sungpack Hong, Sungjoo Yoo, Onur Mutlu, Kiyoung Choi

CoRR, 2023

PaLM 2 Technical Report.

Rohan Anil, Andrew M. Dai, Orhan Firat, Melvin Johnson, Dmitry Lepikhin, Alexandre Passos, Siamak Shakeri, Emanuel Taropa, Paige Bailey, Zhifeng Chen, Eric Chu, Jonathan H. Clark, Laurent El Shafey, Yanping Huang, Kathy Meier-Hellstern, Gaurav Mishra, Erica Moreira, Mark Omernick, Kevin Robinson, Sebastian Ruder, Yi Tay, Kefan Xiao, Yuanzhong Xu, Yujing Zhang, Gustavo Hernández Ábrego, Junwhan Ahn, Jacob Austin, Paul Barham, Jan A. Botha, James Bradbury, Siddhartha Brahma, Kevin Brooks, Michele Catasta, Yong Cheng, Colin Cherry, Christopher A. Choquette-Choo, Aakanksha Chowdhery, Clément Crepy, Shachi Dave, Mostafa Dehghani, Sunipa Dev, Jacob Devlin, Mark Díaz, Nan Du, Ethan Dyer, Vladimir Feinberg, Fangxiaoyu Feng, Vlad Fienber, Markus Freitag, Xavier Garcia, Sebastian Gehrmann, Lucas Gonzalez, et al.

CoRR, 2023

2020

An Imitation Learning Approach for Cache Replacement.

Evan Zheran Liu, Milad Hashemi, Kevin Swersky, Parthasarathy Ranganathan, Junwhan Ahn

Proceedings of the 37th International Conference on Machine Learning, 2020

2019

Software-Defined Far Memory in Warehouse-Scale Computers.

H. Andrés Lagar-Cavilla, Junwhan Ahn, Suleiman Souhlal, Neha Agarwal, Radoslaw Burny, Shakeel Butt, Jichuan Chang, Ashwin Chaugule, Nan Deng, Junaid Shahid, Greg Thelen, Kamil Adam Yurtsever, Yu Zhao, Parthasarathy Ranganathan

Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems, 2019

2018

Nonvolatile Write Buffer-Based Journaling Bypass for Storage Write Reduction in Mobile Devices.

Mungyu Son, Junwhan Ahn, Sungjoo Yoo

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Benzene: An Energy-Efficient Distributed Hybrid Cache Architecture for Manycore Systems.

Namhyung Kim, Junwhan Ahn, Kiyoung Choi, Daniel Sánchez, Donghoon Yoo, Soojung Ryu

ACM Trans. Archit. Code Optim., 2018

ZeNA: Zero-Aware Neural Network Accelerator.

Dongyoung Kim, Junwhan Ahn, Sungjoo Yoo

IEEE Des. Test, 2018

2017

A novel zero weight/activation-aware hardware architecture of convolutional neural network.

Dongyoung Kim, Junwhan Ahn, Sungjoo Yoo

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Making DRAM Stronger Against Row Hammering.

Mungyu Son, Hyunsun Park, Junwhan Ahn, Sungjoo Yoo

Proceedings of the 54th Annual Design Automation Conference, 2017

Weighted-Entropy-Based Quantization for Deep Neural Networks.

Eunhyeok Park, Junwhan Ahn, Sungjoo Yoo

Proceedings of the 2017 IEEE Conference on Computer Vision and Pattern Recognition, 2017

2016

Low-Power Hybrid Memory Cubes With Link Power Management and Two-Level Prefetching.

Junwhan Ahn, Sungjoo Yoo, Kiyoung Choi

IEEE Trans. Very Large Scale Integr. Syst., 2016

Differential Write-Conscious Software Design on Phase-Change Memory: An SQLite Case Study.

Sungkwang Lee, Taemin Lee, Hyunsun Park, Junwhan Ahn, Sungjoo Yoo, Youjip Won, Sunggu Lee

ACM Trans. Design Autom. Electr. Syst., 2016

Prediction Hybrid Cache: An Energy-Efficient STT-RAM Cache Architecture.

Junwhan Ahn, Sungjoo Yoo, Kiyoung Choi

IEEE Trans. Computers, 2016

AIM: Energy-Efficient Aggregation Inside the Memory Hierarchy.

Junwhan Ahn, Sungjoo Yoo, Kiyoung Choi

ACM Trans. Archit. Code Optim., 2016

Zero and data reuse-aware fast convolution for deep neural networks on GPU.

Hyunsun Park, Dongyoung Kim, Junwhan Ahn, Sungjoo Yoo

Proceedings of the Eleventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2016

2015

Locality-aware vertex scheduling for GPU-based graph computation.

Hyunsun Park, Junwhan Ahn, Eunhyeok Park, Sungjoo Yoo

Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015

Energy-efficient exclusive last-level hybrid caches consisting of SRAM and STT-RAM.

Namhyung Kim, Junwhan Ahn, Woong Seo, Kiyoung Choi

Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015

PIM-enabled instructions: a low-overhead, locality-aware processing-in-memory architecture.

Junwhan Ahn, Sungjoo Yoo, Onur Mutlu, Kiyoung Choi

Proceedings of the 42nd Annual International Symposium on Computer Architecture, 2015

A scalable processing-in-memory accelerator for parallel graph processing.

Junwhan Ahn, Sungpack Hong, Sungjoo Yoo, Onur Mutlu, Kiyoung Choi

Proceedings of the 42nd Annual International Symposium on Computer Architecture, 2015

Memory fast-forward: a low cost special function unit to enhance energy efficiency in GPU for big data processing.

Eunhyeok Park, Junwhan Ahn, Sungpack Hong, Sungjoo Yoo, Sunggu Lee

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

A tiny-capacitor-backed non-volatile buffer to reduce storage writes in smartphones.

Mungyu Son, Junwhan Ahn, Sungjoo Yoo

Proceedings of the 2015 International Conference on Hardware/Software Codesign and System Synthesis, 2015

THOR: Orchestrated thermal management of cores and networks in 3D many-core architectures.

Jinho Lee, Junwhan Ahn, Kiyoung Choi, Kyungsu Kang

Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014

LASIC: Loop-Aware Sleepy Instruction Caches Based on STT-RAM Technology.

Junwhan Ahn, Kiyoung Choi

IEEE Trans. Very Large Scale Integr. Syst., 2014

DASCA: Dead Write Prediction Assisted STT-RAM Cache Architecture.

Junwhan Ahn, Sungjoo Yoo, Kiyoung Choi

Proceedings of the 20th IEEE International Symposium on High Performance Computer Architecture, 2014

Dynamic Power Management of Off-Chip Links for Hybrid Memory Cubes.

Junwhan Ahn, Sungjoo Yoo, Kiyoung Choi

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

2013

Isomorphism-Aware Identification of Custom Instructions With I/O Serialization.

Junwhan Ahn, Kiyoung Choi

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Power-Efficient Predication Techniques for Acceleration of Control Flow Execution on CGRA.

Kyuseung Han, Junwhan Ahn, Kiyoung Choi

ACM Trans. Archit. Code Optim., 2013

Write intensity prediction for energy-efficient non-volatile caches.

Junwhan Ahn, Sungjoo Yoo, Kiyoung Choi

Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013

Selectively protecting error-correcting code for area-efficient and reliable STT-RAM caches.

Junwhan Ahn, Sungjoo Yoo, Kiyoung Choi

Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012

Resource-shared custom instruction generation under performance/area constraints.

Di Wu, Junwhan Ahn, Imyong Lee, Kiyoung Choi

Proceedings of the 2012 International Symposium on System on Chip, 2012

A Memetic Quantum-Inspired Evolutionary Algorithm for circuit bipartitioning problem.

Dongwoo Lee, Junwhan Ahn, Kiyoung Choi

Proceedings of the International SoC Design Conference, 2012

Lower-bits cache for low power STT-RAM caches.

Junwhan Ahn, Kiyoung Choi

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2011

An efficient algorithm for isomorphism-aware custom instruction identification for extensible processors.

Junwhan Ahn, Kiyoung Choi

Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis, 2011

A polynomial-time custom instruction identification algorithm based on dynamic programming.

Junwhan Ahn, Imyong Lee, Kiyoung Choi

Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011