Kyungsu Kang

According to our database1, Kyungsu Kang authored at least 23 papers between 2007 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2019
Seamless SoC Verification Using Virtual Platforms: An Industrial Case Study.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2016
Hybrid L2 NUCA Design and Management Considering Data Access Latency, Energy Efficiency, and Storage Lifetime.
IEEE Trans. Very Large Scale Integr. Syst., 2016

A power-efficient 3-D on-chip interconnect for multi-core accelerators with stacked L2 cache.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015
Runtime Thermal Management for 3-D Chip-Multiprocessors With Hybrid SRAM/MRAM L2 Cache.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Cost-Effective Design of Mesh-of-Tree Interconnect for Multicore Clusters With 3-D Stacked L2 Scratchpad Memory.
IEEE Trans. Very Large Scale Integr. Syst., 2015

REDELF: An Energy-Efficient Deadlock-Free Routing for 3D NoCs with Partial Vertical Connections.
ACM J. Emerg. Technol. Comput. Syst., 2015

THOR: Orchestrated thermal management of cores and networks in 3D many-core architectures.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014
Runtime 3-D stacked cache data management for energy minimization of 3-D chip-multiprocessors.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

Temperature-aware runtime power management for chip-multiprocessors with 3-D stacked cache.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

2013
Runtime 3-D stacked cache management for chip-multiprocessors.
Proceedings of the International Symposium on Quality Electronic Design, 2013

2012
A high-throughput and low-latency interconnection network for multi-core Clusters with 3-D stacked L2 tightly-coupled data memory.
Proceedings of the 20th IEEE/IFIP International Conference on VLSI and System-on-Chip, 2012

Cost-effective TSV redundancy configuration.
Proceedings of the 20th IEEE/IFIP International Conference on VLSI and System-on-Chip, 2012

Temperature-aware energy minimization of 3D-stacked L2 DRAM cache through DVFS.
Proceedings of the International SoC Design Conference, 2012

2011
Runtime Power Management of 3-D Multi-Core Architectures Under Peak Power and Temperature Constraints.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Exploiting maximum throughput in 3D multicore architectures with stacked NUCA cache.
Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011

Maximizing throughput of temperature-constrained multi-core systems with 3D-stacked cache memory.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

Thermal-aware energy minimization of 3D-stacked L3 cache with error rate limitation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Design and management of 3D-stacked NUCA cache for chip multiprocessors.
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011

2010
Temperature-Aware Integrated DVFS and Power Gating for Executing Tasks With Runtime Distribution.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Temperature- and bus traffic- aware data placement in 3D-stacked cache.
Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010

2007
Fast estimation of software energy consumption using IPI(Inter-Prefetch Interval) energy model.
Proceedings of the IFIP VLSI-SoC 2007, 2007

Search Area Selective Reuse Algorithm in Motion Estimation.
Proceedings of the 2007 IEEE International Conference on Multimedia and Expo, 2007

Software power estimation using IPI(inter-prefetch interval) power model for advanced off-the-shelf processor.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007


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