Junzhan Liu

According to our database, Junzhan Liu authored at least 11 papers between 2021 and 2026.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2026

A 4/8b High-Precision Fully-Parallel In-Sensor Computing Chip with Subthreshold Digital Pixel and Hybrid Pulse Modulation.

Junda Zhao, Yimo Du, Taoyi Wang, Liang Zhang, Junzhan Liu, He Zhang, Wang Kang

Proceedings of the IEEE International Symposium on Circuits and Systems, 2026

FABS-CIM: Unlocking A/D Conversion Bottlenecks of Bit-Serial Computing-In-Memory with Analog Shift-and-Addition and In-Situ Batch Normalization.

Liang Zhang, Yang Liu, Junda Zhao, Jing Kou, Junzhan Liu, Wang Kang

Proceedings of the IEEE International Symposium on Circuits and Systems, 2026

FALCON: A Fast and Low-Power Current-Mode Near-Sensor-Computing Architecture for Real-Time Edge Visual Processing.

Liang Zhang, Jing Kou, Jinyao Mi, Yang Liu, Junda Zhao, Junzhan Liu, Wang Kang

Proceedings of the Design, Automation & Test in Europe Conference, 2026

2025

ReasoningV: Efficient Verilog Code Generation with Adaptive Hybrid Reasoning Model.

Haiyan Qin, Zhiwei Xie, Jingjing Li, Liangchen Li, Xiaotong Feng, Junzhan Liu, Wang Kang

CoRR, April, 2025

HiT-CIM: A High-Throughput Compute-in-Memory SRAM Architecture With Simultaneous Weight Loading/Computing and Balance Capabilities.

Junzhan Liu, Sifan Sun, Liang Zhang, Lichuan Luo, Liang Ran, He Zhang, Wang Kang, Weisheng Zhao

IEEE Trans. Emerg. Top. Comput., 2025

2024

Erratum to "A Reconfigurable Spatial Architecture for Energy-Efficient Inception Neural Networks".

Lichuan Luo, Wang Kang, Junzhan Liu, He Zhang, Youguang Zhang, Dijun Liu, Peng Ouyang

IEEE J. Emerg. Sel. Topics Circuits Syst., December, 2024

CiTST-AdderNets: Computing in Toggle Spin Torques MRAM for Energy-Efficient AdderNets.

Lichuan Luo, Erya Deng, Dijun Liu, Zhen Wang, Weiliang Huang, He Zhang, Xiao Liu, Jinyu Bai, Junzhan Liu, Youguang Zhang, Wang Kang

IEEE Trans. Circuits Syst. I Regul. Pap., March, 2024

2023

A Reconfigurable Spatial Architecture for Energy-Efficient Inception Neural Networks.

Lichuan Luo, Wang Kang, Junzhan Liu, He Zhang, Youguang Zhang, Dijun Liu, Peng Ouyang

IEEE J. Emerg. Sel. Topics Circuits Syst., March, 2023

2022

HD-CIM: Hybrid-Device Computing-In-Memory Structure Based on MRAM and SRAM to Reduce Weight Loading Energy of Neural Networks.

He Zhang, Junzhan Liu, Jinyu Bai, Sai Li, Lichuan Luo, Shaoqian Wei, Jianxin Wu, Wang Kang

IEEE Trans. Circuits Syst. I Regul. Pap., 2022

CP-SRAM: charge-pulsation SRAM marco for ultra-high energy-efficiency computing-in-memory.

He Zhang, Linjun Jiang, Jianxin Wu, Tingran Chen, Junzhan Liu, Wang Kang, Weisheng Zhao

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2021

A 40nm 33.6Tops/W 8T-SRAM Computing-in-Memory Macro with DAC-less Spike-Pulse-Truncation Input and ADC-less Charge-Reservoir-Integrate-Counter Output.

He Zhang, Junzhan Liu, Wang Kang, Yunqian Fan, Shufeng Fu, Jinyu Bai, Biao Pan, Yongpan Liu, Weisheng Zhao

Proceedings of the 2021 IEEE International Conference on Integrated Circuits, 2021