Sifan Sun

Orcid: 0009-0001-8925-3455

According to our database1, Sifan Sun authored at least 16 papers between 2021 and 2026.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of five.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

On csauthors.net:

Bibliography

2026
High-Efficiency and Low-Deviation Analog-Digital Hybrid Compute-in-Memory Architecture With Dynamic Weight Division.
IEEE Trans. Circuits Syst. I Regul. Pap., June, 2026

A 40 nm Buffer-Free 7T-SRAM Analog Charge-Domain CIM Macro With Merging Timing Based On Time-Row Division Strategy.
IEEE Trans. Very Large Scale Integr. Syst., March, 2026

2025
A Self-Decryption Pass Transistor Logic-Based In-MRAM Computing Macro Using Hybrid VGSOT-MTJ/GAA-CNTFET.
IEEE Trans. Circuits Syst. I Regul. Pap., November, 2025

In-MRAM Computing Based on Complementary-Sensing Time-Based Readout Circuit Using Hybrid VGSOT-MTJ/GAA-CNTFET.
IEEE Trans. Circuits Syst. II Express Briefs, January, 2025

HiT-CIM: A High-Throughput Compute-in-Memory SRAM Architecture With Simultaneous Weight Loading/Computing and Balance Capabilities.
IEEE Trans. Emerg. Top. Comput., 2025

Model quantization for computing-in-memory: a survey.
Sci. China Inf. Sci., 2025

Efficient Weight Mapping and Resource Scheduling on Crossbar-based Multi-core CIM Systems.
Proceedings of the 62nd ACM/IEEE Design Automation Conference, 2025

A 24.65 TOPS/W@INT8 Hybrid Analog-Digital Multi-core SRAM CIM Macro with Optimal Weight Dividing and Resource Allocation Strategies.
Proceedings of the 30th Asia and South Pacific Design Automation Conference, 2025

2024
CIM²PQ: An Arraywise and Hardware-Friendly Mixed Precision Quantization Method for Analog Computing-In-Memory.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., July, 2024

CIMQ: A Hardware-Efficient Quantization Framework for Computing-In-Memory-Based Neural Network Accelerators.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., January, 2024

2023
Partial Sum Quantization for Computing-In-Memory-Based Neural Network Accelerator.
IEEE Trans. Circuits Syst. II Express Briefs, August, 2023

ES-MPQ: Evolutionary Search Enabled Mixed Precision Quantization Framework for Computing-in-Memory.
Proceedings of the 12th Non-Volatile Memory Systems and Applications Symposium, 2023

An In-Memory-Computing STT-MRAM Macro with Analog ReLU and Pooling Layers for Ultra-High Efficient Neural Network.
Proceedings of the 12th Non-Volatile Memory Systems and Applications Symposium, 2023

Exploring Bit-Level Sparsity for Partial Sum Quantization in Computing-In-Memory Accelerator.
Proceedings of the 12th Non-Volatile Memory Systems and Applications Symposium, 2023

Hierarchical Non-Structured Pruning for Computing-In-Memory Accelerators with Reduced ADC Resolution Requirement.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

2021
Tiny neural network search and implementation for embedded FPGA: a software-hardware co-design approach.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021


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