Erya Deng

Orcid: 0000-0001-5064-8057

According to our database1, Erya Deng authored at least 20 papers between 2013 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
CiTST-AdderNets: Computing in Toggle Spin Torques MRAM for Energy-Efficient AdderNets.
IEEE Trans. Circuits Syst. I Regul. Pap., March, 2024

2022
A Spintronic In-Memory Computing Network for Efficient Hamming Codec Implementation.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

2021
A Novel Multi-Context Non-Volatile Content-Addressable Memory Cell and Multi-Level Architecture for High Reliability and Density.
Proceedings of the 10th IEEE Non-Volatile Memory Systems and Applications Symposium, 2021

Fully Single Event Double Node Upset Tolerant Design for Magnetic Random Access Memory.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

SpinSim: A Computer Architecture-Level Variation Aware STT-MRAM Performance Evaluation Framework.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

HSC: A Hybrid Spin/CMOS Logic Based In-Memory Engine with Area-Efficient Mapping Strategy.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

Spin-Orbit Torque Nonvolatile Flip-Flop Designs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

A Reconfigurable Arbiter PUF Based on STT-MRAM.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2019
A Novel MTJ-Based Non-Volatile Ternary Content-Addressable Memory for High-Speed, Low-Power, and High-Reliable Search Operation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

2018
A high-reliability and low-power computing-in-memory implementation within STT-MRAM.
Microelectron. J., 2018

Multi-bit nonvolatile flip-flop based on NAND-like spin transfer torque MRAM.
Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration, 2018

High-Density and Fast-Configuration Non-Volatile Look-Up Table Based on NAND-Like Spintronic Memory.
Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018

2016
Multi-context non-volatile content addressable memory using magnetic tunnel junctions.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016

2015
Synchronous 8-bit Non-Volatile Full-Adder based on Spin Transfer Torque Magnetic Tunnel Junction.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

Robust magnetic full-adder with voltage sensing 2T/2MTJ cell.
Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures, 2015

2014
Synchronous Non-Volatile Logic Gate Design Based on Resistive Switching Memories.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

Ultra Low Power Magnetic Flip-Flop Based on Checkpointing/Power Gating and Self-Enable Mechanisms.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

Compact model of magnetic tunnel junction with stochastic spin transfer torque switching for reliability analyses.
Microelectron. Reliab., 2014

2013
Synchronous full-adder based on complementary resistive switching memory cells.
Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013

Analytical study of complementary memristive synchronous logic gates.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2013


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