Biao Pan
Orcid: 0000-0002-9524-7617
According to our database1,
Biao Pan authored at least 30 papers
between 2000 and 2026.
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Bibliography
2026
IEEE Trans. Circuits Syst. Video Technol., June, 2026
HyIMC: A 16 TOPS/W Hybrid Analog-Digital In-Memory Computing SoC With Model Compression and Recurrent Optimization for Deep Learning-Based Speech Enhancement.
IEEE J. Emerg. Sel. Topics Circuits Syst., June, 2026
STM-CIM: A 2427 TOPS/W Signed Compute-in-Memory with Analog-Domain Top-k and Matrix Transpose for CNN & Transformer.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2026
SuperCIM: A Charge-domain CIM with 3D Parallelism Reconfigurability based on Asynchronous NoC Protocol.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2026
An Operator-Circuit Co-design Digital SOT-MRAM Computing-in-Memory Accelerator with Double Bit Density and Full-Utilized Bandwidth/Throughput.
Proceedings of the Design, Automation & Test in Europe Conference, 2026
2025
Non-Local Mean Denoising of Multi-Layer With Adaptive Filtering Strength Based on ASIC Implementation.
IEEE Trans. Circuits Syst. I Regul. Pap., December, 2025
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025
ACSNN: A 61.25 TOPS/W, 1.65 ns delay SNN Processor that combines CIM-inspired Synapse and Asynchronous Architecture.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025
PAR-CIM: A Precise/Approximate Reconfigurable Digital CIM Macro with 0.35-4b Fractional Mixed-Bitwidth Quantization.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2025
2024
PipeCIM: A High-Throughput Computing-In-Memory Microprocessor With Nested Pipeline and RISC-V Extended Instructions.
IEEE Trans. Circuits Syst. I Regul. Pap., July, 2024
An End-to-End In-Memory Computing System Based on a 40-nm eFlash-Based IMC SoC: Circuits, Toolchains, and Systems Co-Design Framework.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., June, 2024
Toward Energy-efficient STT-MRAM-based Near Memory Computing Architecture for Embedded Systems.
ACM Trans. Embed. Comput. Syst., May, 2024
RDCIM: RISC-V Supported Full-Digital Computing-in-Memory Processor With High Energy Efficiency and Low Area Overhead.
IEEE Trans. Circuits Syst. I Regul. Pap., April, 2024
DS-CIM: A 40nm Asynchronous Dual-Spike Driven, MRAM Compute-In-Memory Macro for Spiking Neural Network.
IEEE Trans. Circuits Syst. I Regul. Pap., April, 2024
Proceedings of the Forty-first International Conference on Machine Learning, 2024
2023
IEEE Trans. Emerg. Top. Comput., 2023
A 40nm 5-16Tops/W@INT8 eFlash In-Memory Computing SoC Chip with Noise Suppression and Compensation Techniques to Improve the Accuracy.
Proceedings of the IEEE International Conference on Integrated Circuits, 2023
2022
IEEE Trans. Circuits Syst. II Express Briefs, 2022
2021
Sci. China Inf. Sci., 2021
HSC: A Hybrid Spin/CMOS Logic Based In-Memory Engine with Area-Efficient Mapping Strategy.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
A 40nm 33.6Tops/W 8T-SRAM Computing-in-Memory Macro with DAC-less Spike-Pulse-Truncation Input and ADC-less Charge-Reservoir-Integrate-Counter Output.
Proceedings of the 2021 IEEE International Conference on Integrated Circuits, 2021
2020
Proceedings of the ICITEE2020: The 3rd International Conference on Information Technologies and Electrical Engineering, 2020
2019
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
2018
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018
2010
Proceedings of the 10th IEEE International Conference on Computer and Information Technology, 2010
2000
Proceedings of the New Approaches in Software Measurement, 10th International Workshop, 2000