He Zhang
Orcid: 0000-0001-9262-3106Affiliations:
- Beihang University, Fert Beijing Insitute, MIIT Key Laboratory of Spintronics, Beijing, China (PhD 2021)
According to our database1,
He Zhang authored at least 41 papers
between 2016 and 2026.
Collaborative distances:
Collaborative distances:
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Bibliography
2026
High-Efficiency and Low-Deviation Analog-Digital Hybrid Compute-in-Memory Architecture With Dynamic Weight Division.
IEEE Trans. Circuits Syst. I Regul. Pap., June, 2026
Self-Calibrating Analog Circuitry for Softmax-Scaled Function With Analog Computing-In-Memory.
IEEE Trans. Very Large Scale Integr. Syst., March, 2026
A 40 nm Buffer-Free 7T-SRAM Analog Charge-Domain CIM Macro With Merging Timing Based On Time-Row Division Strategy.
IEEE Trans. Very Large Scale Integr. Syst., March, 2026
Sci. China Inf. Sci., 2026
A 4/8b High-Precision Fully-Parallel In-Sensor Computing Chip with Subthreshold Digital Pixel and Hybrid Pulse Modulation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2026
Design and Implementation of a Scalable 64 p-bits Ising Computing Chip with Integrated SOT-MTJs for Efficient Computing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2026
A 6.86Tb/s Bandwidth SOT-MRAM Sensing Scheme with Configurable Full-Column Over Frequency Technique for Near Memory Computing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2026
An Effective SNN Macro with Real-Time STDP and Dynamic LIF Model Based on Thermally Interplayed Spin-Orbit Torque MTJ.
Proceedings of the Design, Automation & Test in Europe Conference, 2026
An Operator-Circuit Co-design Digital SOT-MRAM Computing-in-Memory Accelerator with Double Bit Density and Full-Utilized Bandwidth/Throughput.
Proceedings of the Design, Automation & Test in Europe Conference, 2026
2025
A 0.88 e‾<sub>rms</sub> 8-Mpixel 3D-Stacked Low Temporal-Noise CMOS Image Sensor With Auto-Zero Single-Slope ADC, Fast Correlated Multi-Sampling, Row-Wise Noise Reduction, and Dark Current Non-Uniformity Calibration Techniques.
IEEE Trans. Circuits Syst. I Regul. Pap., November, 2025
HiT-CIM: A High-Throughput Compute-in-Memory SRAM Architecture With Simultaneous Weight Loading/Computing and Balance Capabilities.
IEEE Trans. Emerg. Top. Comput., 2025
Thermal-Compensated MRAM Sensing: Dynamic TMR Stabilization Across Wide Temperature Range.
Proceedings of the 14th International Conference on Modern Circuits and Systems Technologies, 2025
An Adaptive Sparse Matrix Compression CIM Accelerator based on 256Kb SOT-MRAM for Downlink Massive MIMO Communications.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2025
A 24.65 TOPS/W@INT8 Hybrid Analog-Digital Multi-core SRAM CIM Macro with Optimal Weight Dividing and Resource Allocation Strategies.
Proceedings of the 30th Asia and South Pacific Design Automation Conference, 2025
2024
Erratum to "A Reconfigurable Spatial Architecture for Energy-Efficient Inception Neural Networks".
IEEE J. Emerg. Sel. Topics Circuits Syst., December, 2024
PipeCIM: A High-Throughput Computing-In-Memory Microprocessor With Nested Pipeline and RISC-V Extended Instructions.
IEEE Trans. Circuits Syst. I Regul. Pap., July, 2024
Toward Energy-efficient STT-MRAM-based Near Memory Computing Architecture for Embedded Systems.
ACM Trans. Embed. Comput. Syst., May, 2024
CiTST-AdderNets: Computing in Toggle Spin Torques MRAM for Energy-Efficient AdderNets.
IEEE Trans. Circuits Syst. I Regul. Pap., March, 2024
MixMixQ: Quantization with Mixed Bit-Sparsity and Mixed Bit-Width for CIM Accelerators.
Proceedings of the Great Lakes Symposium on VLSI 2024, 2024
Series-Parallel Hybrid SOT-MRAM Computing-in-Memory Macro with Multi-Method Modulation for High Area and Energy Efficiency.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024
2023
A Reconfigurable Spatial Architecture for Energy-Efficient Inception Neural Networks.
IEEE J. Emerg. Sel. Topics Circuits Syst., March, 2023
An In-Memory-Computing STT-MRAM Macro with Analog ReLU and Pooling Layers for Ultra-High Efficient Neural Network.
Proceedings of the 12th Non-Volatile Memory Systems and Applications Symposium, 2023
Proceedings of the 18th ACM International Symposium on Nanoscale Architectures, 2023
Toward Energy-Efficient Sparse Matrix-Vector Multiplication with near STT-MRAM Computing Architecture.
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023
2022
SpinCIM: spin orbit torque memory for ternary neural networks based on the computing-in-memory architecture.
CCF Trans. High Perform. Comput., December, 2022
IEEE Trans. Circuits Syst. II Express Briefs, 2022
IEEE Trans. Circuits Syst. II Express Briefs, 2022
HD-CIM: Hybrid-Device Computing-In-Memory Structure Based on MRAM and SRAM to Reduce Weight Loading Energy of Neural Networks.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
CP-SRAM: charge-pulsation SRAM marco for ultra-high energy-efficiency computing-in-memory.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022
2021
A 40nm 33.6Tops/W 8T-SRAM Computing-in-Memory Macro with DAC-less Spike-Pulse-Truncation Input and ADC-less Charge-Reservoir-Integrate-Counter Output.
Proceedings of the 2021 IEEE International Conference on Integrated Circuits, 2021
SpinLiM: Spin Orbit Torque Memory for Ternary Neural Networks Based on the Logic-in-Memory Architecture.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
2020
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020
High-Density, Low-Power Voltage-Control Spin Orbit Torque Memory with Synchronous Two-Step Write and Symmetric Read Techniques.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
2019
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2019
2018
IEEE Access, 2018
A Novel Cross-point MRAM with Diode Selector Capable of High-Density, High-Speed, and Low-Power In-Memory Computation.
Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures, 2018
High-Density and Fast-Configuration Non-Volatile Look-Up Table Based on NAND-Like Spintronic Memory.
Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018
2017
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017
2016
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016