He Zhang

Orcid: 0000-0001-9262-3106

Affiliations:
  • Beihang University, Fert Beijing Insitute, MIIT Key Laboratory of Spintronics, Beijing, China (PhD 2021)


According to our database1, He Zhang authored at least 20 papers between 2016 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
CiTST-AdderNets: Computing in Toggle Spin Torques MRAM for Energy-Efficient AdderNets.
IEEE Trans. Circuits Syst. I Regul. Pap., March, 2024

2023
A Reconfigurable Spatial Architecture for Energy-Efficient Inception Neural Networks.
IEEE J. Emerg. Sel. Topics Circuits Syst., March, 2023

An In-Memory-Computing STT-MRAM Macro with Analog ReLU and Pooling Layers for Ultra-High Efficient Neural Network.
Proceedings of the 12th Non-Volatile Memory Systems and Applications Symposium, 2023

A Robust Time-based Error-Proofing Readout Scheme for MRAM.
Proceedings of the 18th ACM International Symposium on Nanoscale Architectures, 2023

2022
SpinCIM: spin orbit torque memory for ternary neural networks based on the computing-in-memory architecture.
CCF Trans. High Perform. Comput., December, 2022

A Mini Tutorial of Processing in Memory: From Principles, Devices to Prototypes.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

A Spintronic In-Memory Computing Network for Efficient Hamming Codec Implementation.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

HD-CIM: Hybrid-Device Computing-In-Memory Structure Based on MRAM and SRAM to Reduce Weight Loading Energy of Neural Networks.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022

CP-SRAM: charge-pulsation SRAM marco for ultra-high energy-efficiency computing-in-memory.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2021
A 40nm 33.6Tops/W 8T-SRAM Computing-in-Memory Macro with DAC-less Spike-Pulse-Truncation Input and ADC-less Charge-Reservoir-Integrate-Counter Output.
Proceedings of the 2021 IEEE International Conference on Integrated Circuits, 2021

SpinLiM: Spin Orbit Torque Memory for Ternary Neural Networks Based on the Logic-in-Memory Architecture.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020
Deep Neural Network accelerator with Spintronic Memory.
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

High-Density, Low-Power Voltage-Control Spin Orbit Torque Memory with Synchronous Two-Step Write and Symmetric Read Techniques.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019
Spintronic Memories: From Memory to Computing-in-Memory.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2019

2018
A Full-Sensing-Margin Dual-Reference Sensing Scheme for Deeply-Scaled STT-RAM.
IEEE Access, 2018

A Novel Cross-point MRAM with Diode Selector Capable of High-Density, High-Speed, and Low-Power In-Memory Computation.
Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures, 2018

High-Density and Fast-Configuration Non-Volatile Look-Up Table Based on NAND-Like Spintronic Memory.
Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018

2017
Programmable Stateful In-Memory Computing Paradigm via a Single Resistive Device.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

Advanced Low Power Spintronic Memories beyond STT-MRAM.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

2016
Dual reference sensing scheme with triple steady states for deeply scaled STT-MRAM.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016


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