Klaus Schneider
Orcid: 0000-0002-1305-7132Affiliations:
- University of Kaiserslautern, Department of Computer Science, Germany
According to our database1,
Klaus Schneider
authored at least 224 papers
between 1981 and 2023.
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Bibliography
2023
Consistency Constraints for Mapping Dataflow Graphs to Hybrid Dataflow/von Neumann Architectures.
ACM Trans. Embed. Comput. Syst., September, 2023
Proceedings of the 16th International Workshop on Network on Chip Architectures, 2023
Proceedings of the 21st ACM-IEEE International Symposium on Formal Methods and Models for System Design, 2023
Allocation and Scheduling of Dataflow Graphs on Hybrid Dataflow/von Neumann Architectures.
Proceedings of the 21st ACM-IEEE International Symposium on Formal Methods and Models for System Design, 2023
Proceedings of the Methods and Description Languages for Modelling and Verification of Circuits and Systems, 2023
Formal Methods-Based Optimization of Dataflow Models with Translation to Synchronous Models.
Proceedings of the Forum on Specification & Design Languages, 2023
Proceedings of the 47th IEEE Annual Computers, Software, and Applications Conference, 2023
2022
SN Comput. Sci., 2022
Proceedings of the 15th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2022
Proceedings of the Methods and Description Languages for Modelling and Verification of Circuits and Systems, 2022
Proceedings of the Methods and Description Languages for Modelling and Verification of Circuits and Systems, 2022
Code generation criteria for buffered exposed datapath architectures from dataflow graphs.
Proceedings of the LCTES '22: 23rd ACM SIGPLAN/SIGBED International Conference on Languages, 2022
Proceedings of the Forum on Specification & Design Languages, 2022
2021
Integrating Kahn Process Networks as a Model of Computation in an Extendable Model-based Design Framework.
Proceedings of the 9th International Conference on Model-Driven Engineering and Software Development, 2021
Proceedings of the MEMOCODE '21: 19th ACM-IEEE International Conference on Formal Methods and Models for System Design, Virtual Event, China, November 20, 2021
Proceedings of the MEMOCODE '21: 19th ACM-IEEE International Conference on Formal Methods and Models for System Design, Virtual Event, China, November 20, 2021
Efficient Implementation of Heterogeneous Dataflow Models using Synchronous IO Patterns.
Proceedings of the 24th Euromicro Conference on Digital System Design, 2021
A Model-based Design Flow for Asynchronous Implementations from Synchronous Specifications.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
Proceedings of the IEEE 45th Annual Computers, Software, and Applications Conference, 2021
2020
Compiling synchronous languages to optimal move code for exposed datapath architectures.
Proceedings of the SCOPES '20: 23rd International Workshop on Software and Compilers for Embedded Systems, 2020
Employing OpenCL as a Standard Hardware Abstraction in a Distributed Embedded System: A Case Study.
Proceedings of the 9th Mediterranean Conference on Embedded Computing, 2020
Proceedings of the 23rd GMM/ITG/GI Workshop on Methods and Description Languages for Modelling and Verification of Circuits and Systems, 2020
Proceedings of the 23rd GMM/ITG/GI Workshop on Methods and Description Languages for Modelling and Verification of Circuits and Systems, 2020
SHeD: A Framework for Automatic Software Synthesis of Heterogeneous Dataflow Process Networks.
Proceedings of the 23rd Euromicro Conference on Digital System Design, 2020
2019
Guest Editorial: Special Issue of ACM TECS on the ACM-IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE 2017).
ACM Trans. Embed. Comput. Syst., 2019
Evaluating OpenCL as a Standard Hardware Abstraction for a Model-based Synthesis Framework: A Case Study.
Proceedings of the 7th International Conference on Model-Driven Engineering and Software Development, 2019
Proceedings of the Joint Proceedings of the Workshop on Model-Driven Engineering for the Internet of Things (MDE4IoT) & of the Workshop on Interplay of Model-Driven and Component-Based Software Engineering (ModComp) Co-located with the IEEE/ACM 22nd International Conference on Model Driven Engineering Languages and Systems (MODELS 2019), 2019
Proceedings of the 22nd Workshop Methods and Description Languages for Modelling and Verification of Circuits and Systems, 2019
Proceedings of the Algorithms and Architectures for Parallel Processing, 2019
Proceedings of the 22nd Euromicro Conference on Digital System Design, 2019
Proceedings of the 19th International Conference on Application of Concurrency to System Design, 2019
2018
Optimal Scheduling for Exposed Datapath Architectures with Buffered Processing Units by ASP.
Theory Pract. Log. Program., 2018
The Half Cleaner Lemma: Constructing Efficient Interconnection Networks from Sorting Networks.
Parallel Process. Lett., 2018
Int. J. Crit. Comput. Based Syst., 2018
Proceedings of the 13th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2018
Proceedings of the 16th ACM/IEEE International Conference on Formal Methods and Models for System Design, 2018
Routing Partial Permutations in General Interconnection Networks based on Radix Sorting.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 2018
Proceedings of the International Conference on Internet of Things, 2018
Proceedings of the Principled Software Development, 2018
Proceedings of the Architecture of Computing Systems - ARCS 2018, 2018
On Memory Optimal Code Generation for Exposed Datapath Architectures with Buffered Processing Units.
Proceedings of the 18th International Conference on Application of Concurrency to System Design, 2018
2017
Proceedings of the Handbook of Hardware/Software Codesign., 2017
Exploring different execution paradigms in exposed datapath architectures with buffered processing units.
Proceedings of the 2017 International Conference on Embedded Computer Systems: Architectures, 2017
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2017
Proceedings of the 10th International Workshop on Network on Chip Architectures, 2017
Proceedings of the Logic Programming and Nonmonotonic Reasoning, 2017
Out-of-Order Execution of Buffered Function Units in Exposed Data Path Architectures.
Proceedings of the 2017 IEEE International Parallel and Distributed Processing Symposium Workshops, 2017
Exploring the Potential of Instruction-Level Parallelism of Exposed Datapath Architectures with Buffered Processing Units.
Proceedings of the 17th International Conference on Application of Concurrency to System Design, 2017
2016
Proceedings of the 10th Workshop on Verification and Evaluation of Computer and Communication System, 2016
Towards the standardization of plug-and-play devices for model-based designs of embedded systems.
Proceedings of the 11th IEEE Symposium on Industrial Embedded Systems, 2016
Introducing MoC Drivers for the Integration of Sensor-Actuator Behaviors in Model-Based Design Flows of Embedded Systems.
Proceedings of the 19th International Workshop on Software and Compilers for Embedded Systems, 2016
The selector-tree network: A new self-routing and non-blocking interconnection network.
Proceedings of the 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2016
Control-flow guided property directed reachability for imperative synchronous programs.
Proceedings of the 2016 ACM/IEEE International Conference on Formal Methods and Models for System Design, 2016
Proceedings of the 2016 ACM/IEEE International Conference on Formal Methods and Models for System Design, 2016
Optimal compilation for exposed datapath architectures with buffered processing units by SAT solvers.
Proceedings of the 2016 ACM/IEEE International Conference on Formal Methods and Models for System Design, 2016
Proceedings of the 19th GI/ITG/GMM Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 2016
Towards Code Generation for the Synchronous Control Asynchronous Dataflow (SCAD) Architectures.
Proceedings of the 19th GI/ITG/GMM Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 2016
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2016
2015
ACM Trans. Embed. Comput. Syst., 2015
Evaluation of Speculation in Out-of-Order Execution of Synchronous Dataflow Networks.
Int. J. Parallel Program., 2015
An SMT-based Approach to analyze Non-Linear Relations of Parameters for Hybrid Systems.
Proceedings of the Formal Modeling and Verification of Cyber-Physical Systems, 2015
Proceedings of the 2015 IEEE Real-Time Systems Symposium, 2015
Proceedings of the 13. ACM/IEEE International Conference on Formal Methods and Models for Codesign, 2015
A Counterexample-Guided Approach to Symbolic Simulation of Hybrid Systems.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 2015
2014
Representation of synchronous, asynchronous, and polychronous components by clocked guarded actions.
Des. Autom. Embed. Syst., 2014
Proceedings of the 2014 Spring Simulation Multiconference, 2014
Proceedings of the SOFSEM 2014: Theory and Practice of Computer Science, 2014
Reducing the Communication of Message-Passing Systems Synthesized from Synchronous Programs.
Proceedings of the 22nd Euromicro International Conference on Parallel, 2014
Proceedings of the MODELSWARD 2014 - Proceedings of the 2nd International Conference on Model-Driven Engineering and Software Development, Lisbon, Portugal, 7, 2014
Proceedings of the Twelfth ACM/IEEE International Conference on Formal Methods and Models for Codesign, 2014
Synthesis of Distributed Synchronous Specifications to SysteMoC.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 2014
Using Different Representations of Synchronous Systems in SAL.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 2014
Proceedings of the 22nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2014
Proceedings of the Workshop on Embedded and Cyber-Physical Systems Education, 2014
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
2013
Proceedings of the Software Engineering and Formal Methods - 11th International Conference, 2013
Proceedings of the International Workshop on Software and Compilers for Embedded Systems, 2013
Targeting different abstraction layers by model-based design methods for embedded systems: A case study.
Proceedings of the 2013 IEEE 19th International Conference on Embedded and Real-Time Computing Systems and Applications, 2013
Proceedings of the 11th ACM/IEEE International Conference on Formal Methods and Models for Codesign, 2013
An Interactive Verification Tool for Synchronous/Reactive Systems.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2013
Proceedings of the Integrated Formal Methods, 10th International Conference, 2013
Proceedings of the 2013 Federated Conference on Computer Science and Information Systems, 2013
Interactive Verification of Cyber-physical Systems: Interfacing Averest and KeYmaera.
Proceedings of the 2013 Federated Conference on Computer Science and Information Systems, 2013
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013
Proceedings of the 13th International Conference on Application of Concurrency to System Design, 2013
2012
Proceedings of the 2012 International Conference on Embedded Computer Systems: Architectures, 2012
Proceedings of the sixth workshop on Programming Languages meets Program Verification, 2012
Proceedings of the Tenth ACM/IEEE International Conference on Formal Methods and Models for Codesign, 2012
Proceedings of the Tenth ACM/IEEE International Conference on Formal Methods and Models for Codesign, 2012
Proceedings of the Logic for Programming, Artificial Intelligence, and Reasoning, 2012
Proceedings of the 14th IEEE International Conference on High Performance Computing and Communication & 9th IEEE International Conference on Embedded Software and Systems, 2012
Proceedings of the 2012 IEEE International High Level Design Validation and Test Workshop, 2012
Proceedings of the Workshop on Embedded and Cyber-Physical Systems Education, 2012
2011
A uniform approach to three-valued semantics for <i>μ</i>-calculus on abstractions of hybrid automata.
Int. J. Softw. Tools Technol. Transf., 2011
Proceedings of the Proceedings International Workshop on Interactions, Games and Protocols, 2011
Proceedings of the Model Checking Software, 2011
Proceedings of the 14th International Workshop on Software and Compilers for Embedded Systems, 2011
Proceedings of the 12th International Conference on Parallel and Distributed Computing, 2011
Synthesis of Parallel Sorting Networks using SAT Solvers.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2011
Round Trip to Asynchrony and Synchrony.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2011
Proceedings of the Knowledge-Based and Intelligent Information and Engineering Systems, 2011
Proceedings of the IEEE 29th International Conference on Computer Design, 2011
Proceedings of the 2011 IEEE International High Level Design Validation and Test Workshop, 2011
Proceedings of the 2011 Forum on Specification & Design Languages, 2011
Proceedings of the 2011 Forum on Specification & Design Languages, 2011
Proceedings of the 11th International Conference on Application of Concurrency to System Design, 2011
2010
Exploiting the Temporal Logic Hierarchy and the Non-Confluence Property for Efficient LTL Synthesis
Proceedings of the Proceedings First Symposium on Games, 2010
Proceedings of the 8th ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE 2010), 2010
Proceedings of the 8th ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE 2010), 2010
From Synchronous Guarded Actions to SystemC.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2010
Multithreaded Code from Synchronous Programs: Generating Software Pipelines for OpenMP.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2010
Translating concurrent action oriented specifications to synchronous guarded actions.
Proceedings of the ACM SIGPLAN/SIGBED 2010 conference on Languages, 2010
Proceedings of the Distributed, Parallel and Biologically Inspired Systems, 2010
Proceedings of the 13th ACM International Conference on Hybrid Systems: Computation and Control, 2010
Multithreaded code from synchronous programs: Extracting independent threads for OpenMP.
Proceedings of the Design, Automation and Test in Europe, 2010
Proceedings of the 10th International Conference on Application of Concurrency to System Design, 2010
Proceedings of the 10th International Conference on Application of Concurrency to System Design, 2010
Proceedings of the 10th IEEE International Conference on Computer and Information Technology, 2010
2009
Proceedings of the Logic, 2009
Proceedings of the 12th International Workshop on Software and Compilers for Embedded Systems, 2009
Proceedings of the 7th ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE 2009), 2009
Using IP Cores in Synchronous Languages.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2009
Proceedings of the Design, Automation and Test in Europe, 2009
Proceedings of the SYNCHRON 2009, 22.11. - 27.11.2009, 2009
Online Exercise System - A Web-based Tool for Administration and Automatic Correction of Exercises.
Proceedings of the CSEDU 2009 - Proceedings of the First International Conference on Computer Supported Education, Lisboa, Portugal, March 23-26, 2009, 2009
Proceedings of the Ninth International Conference on Application of Concurrency to System Design, 2009
2008
Proceedings of the Second Workshop on Reachability Problems in Computational Models, 2008
Proceedings of the Verification, 2008
Proceedings of the Theorem Proving in Higher Order Logics, 21st International Conference, 2008
Generating Deterministic $\omega$-Automata for most LTL Formulas by the Breakpoint Construction.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2008
Hardware Acceleration for Model Checking.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2008
A Uniform Approach to Three-Valued Semantics for µ-Calculus on Abstractions of Hybrid Automata.
Proceedings of the Hardware and Software: Verification and Testing, 2008
Proceedings of the 8th International Conference on Application of Concurrency to System Design (ACSD 2008), 2008
2007
Combining Interval Arithmetic and Three-Valued Temporal Logics for the Verification of Analog Systems.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2007
Proceedings of the Logical Foundations of Computer Science, International Symposium, 2007
Formal verification of safety behaviours of the outdoor robot ravon.
Proceedings of the ICINCO 2007, 2007
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007
How Different are Esterel and SystemC?.
Proceedings of the Forum on specification and Design Languages, 2007
2006
Proceedings of the International Symposium on Industrial Embedded Systems, 2006
Proceedings of the 4th ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2006), 2006
A Framework for Verifying and Implementing Embedded Systems.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2006
Proceedings of the From Model-Driven Design to Resource Management for Distributed Embedded Systems, 2006
Proceedings of the 2006 international workshop on Self-adaptation and self-managing systems, 2006
Proceedings of the Hardware and Software, 2006
Proceedings of the Forum on specification and Design Languages, 2006
2005
ACM Trans. Embed. Comput. Syst., 2005
Proceedings of the Theorem Proving in Higher Order Logics, 18th International Conference, 2005
Proceedings of the 3rd ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2005), 2005
Synthesizing deterministic controllers in supervisory control.
Proceedings of the ICINCO 2005, 2005
Proceedings of the Formal Methods and Software Engineering, 2005
A unified model checking framework for the supervisor synthesis problem.
Proceedings of the 1st Workshop on Games for Logic and Programming Languages, 2005
Proceedings of the Embedded and Ubiquitous Computing, 2005
Proceedings of the 44th IEEE IEEE Conference on Decision and Control and 8th European Control Conference Control, 2005
Proceedings of the Fifth International Conference on Application of Concurrency to System Design (ACSD 2005), 2005
2004
Texts in Theoretical Computer Science. An EATCS Series, Springer, ISBN: 978-3-662-10778-2, 2004
Proceedings of the Third International Workshop on Synchronous Languages, 2004
Global vs. Local Model Checking: A Comparison of Verification Techniques for Infinite State Systems.
Proceedings of the 2nd International Conference on Software Engineering and Formal Methods (SEFM 2004), 2004
Proceedings of the 2nd ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2004), 2004
Global vs. Local Model Checking of Infinite State Systems.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2004
Proceedings of the 41th Design Automation Conference, 2004
Proceedings of the 2004 International Conference on Compilers, 2004
2003
Proceedings of the 16th Annual Symposium on Integrated Circuits and Systems Design, 2003
Generating Formal Models for Real-Time Verification by Exact Low-Level Runtime Analysis of Synchronous Programs.
Proceedings of the 24th IEEE Real-Time Systems Symposium (RTSS 2003), 2003
Proceedings of the 1st ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2003), 2003
Proceedings of the 1st ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2003), 2003
A μ-Calculus Approach to Supervisor Synthesis.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2003
Exact Low-Level Runtime Analysis of Synchronous Programs for Formal Verification of Real-Time Systems.
Proceedings of the Forum on specification and Design Languages, 2003
Exact High Level WCET Analysis of Synchronous Programs by Symbolic State Space Exploration.
Proceedings of the 2003 Design, 2003
2002
Fundam. Informaticae, 2002
Proceedings of the Theorem Proving in Higher Order Logics, 15th International Conference, 2002
Symbolic Model Checking by Automata Based Set Representation.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2002
Proceedings of the 2002 Design, 2002
2001
Proceedings of the Eigth International Symposium on Temporal Representation and Reasoning, 2001
Improving Automata Generation for Linear Temporal Logic by Considering the Automaton Hierarchy.
Proceedings of the Logic for Programming, 2001
Proceedings of the 13th Euromicro Conference on Real-Time Systems (ECRTS 2001), 2001
Proceedings of the 2nd International Conference on Application of Concurrency to System Design (ACSD 2001), 2001
2000
Proceedings of the Formal Methods Elsewhere, 2000
A Verified Hardware Synthesis of Esterel Programs.
Proceedings of the Architecture and Design of Distributed Embedded Systems, 2000
Proceedings of the 2000 Design, 2000
1999
Proceedings of the Theorem Proving in Higher Order Logics, 12th International Conference, 1999
Abstraction of Systems with Counters for Symbolic Model Checking.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 1999
Translating a Visual Description Technique to a Synchronous Language: From DiChartsto PURR.
Proceedings of the Formale Beschreibungstechniken für verteilte Systeme, 1999
Proceedings of the Perspectives of System Informatics, 1999
Proceedings of the 1999 Design, 1999
Proceedings of the Correct Hardware Design and Verification Methods, 1999
Proceedings of the Correct Hardware Design and Verification Methods, 1999
1998
Kontrollfluss-Verifikation von Algorithmen mittels Modellprüfung.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 1998
A Synchronous Language for Modeling and Verifying Real Time and Embedded Systems.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 1998
Modeling and Verifying Abstract Multithreaded Systems.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 1998
Comparing Model Checking and Term Rewriting for the Verification of an Embedded System.
Proceedings of the Distributed and Parallel Embedded Systems, 1998
Proceedings of the Formal Methods in Computer-Aided Design, 1998
Proceedings of the 1998 Design, 1998
1997
Proceedings of the Formal Hardware Verification - Methods and Systems in Comparison, 1997
1996
Proceedings of the Formal Methods in Computer-Aided Design, First International Conference, 1996
Ein einheitlicher Ansatz zur Unterstützung von Abstraktionsmechanismen der Hardware-Verifikation.
DISKI 116, Infix, ISBN: 978-3-89601-116-9, 1996
1995
Proceedings of the 8th International Conference on VLSI Design (VLSI Design 1995), 1995
1994
Formal Methods Syst. Des., 1994
Proceedings of the Higher Order Logic Theorem Proving and Its Applications, 1994
Proceedings of the Theorem Provers in Circuit Design, 1994
Control Path Oriented Verification of Sequential Generic Circuits with Control and Data Path.
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994
1993
Structuring and Automating Hardware Proofs in a Higher-Order Theorem-Proving Environment.
Formal Methods Syst. Des., 1993
Eliminating Higher-Order Quantifiers to Obtain Decision Procedures for Hardware Verification.
Proceedings of the Higher Order Logic Theorem Proving and its Applications, 1993
Proceedings of the Higher Order Logic Theorem Proving and its Applications, 1993
Proceedings of the Higher Order Logic Theorem Proving and its Applications, 1993
Hardware-Verification using First Order BDDs.
Proceedings of the Computer Hardware Description Languages and their Applications, Proceedings of the 11th IFIP WG10.2 International Conference on Computer Hardware Description Languages and their Applications, 1993
Proceedings of the Correct Hardware Design and Verification Methods, 1993
1992
Modelling Generic Hardware Structures by Abstract Datatypes.
Proceedings of the Higher Order Logic Theorem Proving and its Applications, 1992
Efficient Representation and Computation of Tableau Proofs.
Proceedings of the Higher Order Logic Theorem Proving and its Applications, 1992
1991
Structure in Hardware Proofs: First Steps Towards Automation in a Higher-Order Environment.
Proceedings of the VLSI 91, 1991
First Steps Towards Automating Hardware Proofs in HOL.
Proceedings of the 1991 International Workshop on the HOL Theorem Proving System and its Applications, 1991
Integrating a First-Order Automatic Prover in the HOL Environment.
Proceedings of the 1991 International Workshop on the HOL Theorem Proving System and its Applications, 1991
Proceedings of the Computer Aided Verification, 3rd International Workshop, 1991
1981
Ein System-Diagnoseprozessor für zentralen und dezentralen Einsatz in Prozeßrechner-Systemen.
Proceedings of the Fachtagung Prozeßrechner 1981, 1981