Kavita Nair

According to our database, Kavita Nair authored at least 4 papers between 1999 and 2011.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2011

A 45 nm SOI Embedded DRAM Macro for the POWER™ Processor 32 MByte On-Chip L3 Cache.

John Barth, Don Plass, Erik Nelson, Charlie Hwang, Gregory Fredeman, Michael A. Sperling, Abraham Mathews, Toshiaki Kirihata, William R. Reohr, Kavita Nair, Nianzheng Cao

IEEE J. Solid State Circuits, 2011

2010

A 45nm SOI embedded DRAM macro for POWER7TM 32MB on-chip L3 cache.

John Barth, Don Plass, Erik Nelson, Charlie Hwang, Gregory Fredeman, Michael A. Sperling, Abraham Mathews, William R. Reohr, Kavita Nair, Nianzheng Cao

Proceedings of the IEEE International Solid-State Circuits Conference, 2010

1999

Compact, Ultra Low Power, Programmable Continuous-Time Filter Banks for Feedback Cancellation in Hearing Aid.

Kavita Nair, Ramesh Harjani

Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

A telemetry and interface circuit for piezoelectric sensors.

Kavita Nair, Ramesh Harjani

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999