William R. Reohr

According to our database1, William R. Reohr authored at least 10 papers between 1993 and 2011.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2011
A 45 nm SOI Embedded DRAM Macro for the POWER™ Processor 32 MByte On-Chip L3 Cache.
IEEE J. Solid State Circuits, 2011

2010
A 45nm SOI embedded DRAM macro for POWER7TM 32MB on-chip L3 cache.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2009
A 1 MB Cache Subsystem Prototype With 1.8 ns Embedded DRAMs in 45 nm SOI CMOS.
IEEE J. Solid State Circuits, 2009

Statistical yield analysis of silicon-on-insulator embedded DRAM.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

2008
Rethinking Refresh: Increasing Availability and Reducing Power in DRAM for Cache Applications.
IEEE Micro, 2008

A 500 MHz Random Cycle, 1.5 ns Latency, SOI Embedded DRAM Macro Featuring a Three-Transistor Micro Sense Amplifier.
IEEE J. Solid State Circuits, 2008

An on-chip dual supply charge pump system for 45nm PD SOI eDRAM.
Proceedings of the ESSCIRC 2008, 2008

2007
A 500MHz Random Cycle 1.5ns-Latency, SOI Embedded DRAM Macro Featuring a 3T Micro Sense Amplifier.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2006
Memories: Exploiting Them and Developing Them.
Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006

1993
Design SRAMs for burn-in.
Proceedings of the 11th IEEE VLSI Test Symposium (VTS'93), 1993


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