Gregory Fredeman

According to our database1, Gregory Fredeman authored at least 11 papers between 2007 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2021
Cores, Cache, Content, and Characterization: IBM's Second Generation 14-nm Product, z15.
IEEE J. Solid State Circuits, 2021

2020
IBM z15: Physical design improvements to significantly increase content in the same technology.
IBM J. Res. Dev., 2020


2016
A 14 nm 1.1 Mb Embedded DRAM Macro With 1 ns Access.
IEEE J. Solid State Circuits, 2016

2015

17.4 A 14nm 1.1Mb embedded DRAM macro with 1ns access.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2011
A 45 nm SOI Embedded DRAM Macro for the POWER™ Processor 32 MByte On-Chip L3 Cache.
IEEE J. Solid State Circuits, 2011

2010
A 45nm SOI embedded DRAM macro for POWER7TM 32MB on-chip L3 cache.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2009
A 1 MB Cache Subsystem Prototype With 1.8 ns Embedded DRAMs in 45 nm SOI CMOS.
IEEE J. Solid State Circuits, 2009

2008
A 500 MHz Random Cycle, 1.5 ns Latency, SOI Embedded DRAM Macro Featuring a Three-Transistor Micro Sense Amplifier.
IEEE J. Solid State Circuits, 2008

2007
A 500MHz Random Cycle 1.5ns-Latency, SOI Embedded DRAM Macro Featuring a 3T Micro Sense Amplifier.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007


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