Kazutaka Mori

According to our database, Kazutaka Mori authored at least 5 papers between 1998 and 2014.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2014

28 nm 50% Power-Reducing Contacted Mask Read Only Memory Macro With 0.72-ns Read Access Time Using 2T Pair Bitcell and Dynamic Column Source Bias Control Technique.

Yukiko Umemoto, Koji Nii, Jiro Ishikawa, Makoto Yabuuchi, Kazuyoshi Okamoto, Yasumasa Tsukamoto, Shinji Tanaka, Koji Tanaka, Tetsuya Matsumura, Kazutaka Mori, Kazumasa Yanagisawa

IEEE Trans. Very Large Scale Integr. Syst., 2014

2011

A 28 nm 50% power reduced 2T mask ROM with 0.72 ns read access time using column source bias.

Yukiko Umemoto, Koji Nii, Jiro Ishikawa, Kazuyoshi Okamoto, Kazutaka Mori, Kazumasa Yanagisawa

Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

2001

Design methodology of high performance microprocessor using ultra-low threshold voltage CMOS.

Tamotsu Miyake, Takeo Yamashita, Norikatsu Asari, Hideki Sekisaka, Tom Sakai, Kazuhiro Matsuura, Atsushi Wakahara, Hideyuki Takahashi, Tom Hiyama, Kazuhisa Miyamoto, Kazutaka Mori

Proceedings of the IEEE 2001 Custom Integrated Circuits Conference, 2001

1998

A new optimization strategy for CMOS device process in the era of 0.2 μm and beyond for MPU's and ASIC's.

Kazutaka Mori, Ken'ichi Kikushima, Fumio Ootsuka, Shin'ichiro Mitani

Proceedings of the IEEE 1998 Custom Integrated Circuits Conference, 1998

TCAD/DA for MPU and ASIC Development.

Hiroo Masuda, Katsumi Tsuneno, Hisako Sato, Kazutaka Mori

Proceedings of the ASP-DAC '98, 1998