Hiroo Masuda

According to our database, Hiroo Masuda authored at least 31 papers between 1985 and 2010.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2010

A New LDMOS Transistor Macro-Modeling for Accurately Predicting Bias Dependence of Gate-Overlap Capacitance.

Takashi Sato, Toshiki Kanamoto, Saiko Kobayashi, Nobuhiko Goto, Takao Sato, Hitoshi Sugihara, Hiroo Masuda

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010

Impact of Self-Heating in Wire Interconnection on Timing.

Toshiki Kanamoto, Takaaki Okumura, Katsuhiro Furukawa, Hiroshi Takafuji, Atsushi Kurokawa, Koutaro Hachiya, Tsuyoshi Sakata, Masakazu Tanaka, Hidenari Nakashima, Hiroo Masuda, Takashi Sato, Masanori Hashimoto

IEICE Trans. Electron., 2010

2009

An Approach for Reducing Leakage Current Variation due to Manufacturing Variability.

Tsuyoshi Sakata, Takaaki Okumura, Atsushi Kurokawa, Hidenari Nakashima, Hiroo Masuda, Takashi Sato, Masanori Hashimoto, Koutaro Hachiya, Katsuhiro Furukawa, Masakazu Tanaka, Hiroshi Takafuji, Toshiki Kanamoto

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

Improvement in Computational Accuracy of Output Transition Time Variation Considering Threshold Voltage Variations.

Takaaki Okumura, Atsushi Kurokawa, Hiroo Masuda, Toshiki Kanamoto, Masanori Hashimoto, Hiroshi Takafuji, Hidenari Nakashima, Nobuto Ono, Tsuyoshi Sakata, Takashi Sato

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

Comprehensive Matching Characterization of Analog CMOS Circuits.

Hiroo Masuda, Takeshi Kida, Shin-ichi Ohkawa

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

2008

A Novel Expression of Spatial Correlation by a Random Curved Surface Model and Its Application to LSI Design.

Shin-ichi Ohkawa, Hiroo Masuda, Yasuaki Inoue

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

Concise Modeling of Transistor Variations in an LSI Chip and Its Application to SRAM Cell Sensitivity Analysis.

Masakazu Aoki, Shin-ichi Ohkawa, Hiroo Masuda

IEICE Trans. Electron., 2008

2006

Determination of Interconnect Structural Parameters for Best- and Worst-Case Delays.

Atsushi Kurokawa, Hiroo Masuda, Junko Fujii, Toshinori Inoshita, Akira Kasebe, Zhangcai Huang, Yasuaki Inoue

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

Formula-Based Method for Capacitance Extraction of Interconnects with Dummy Fills.

Atsushi Kurokawa, Akira Kasebe, Toshiki Kanamoto, Yun Yang, Zhangcai Huang, Yasuaki Inoue, Hiroo Masuda

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

2005

A Practical Approach for Efficiently Extracting Interconnect Capacitances with Floating Dummy Fills.

Atsushi Kurokawa, Toshiki Kanamoto, Akira Kasebe, Yasuaki Inoue, Hiroo Masuda

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005

Efficient Dummy Filling Methods to Reduce Interconnect Capacitance and Number of Dummy Metal Fills.

Atsushi Kurokawa, Toshiki Kanamoto, Tetsuya Ibe, Akira Kasebe, Wei Fong Chang, Tetsuro Kage, Yasuaki Inoue, Hiroo Masuda

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005

Second-Order Polynomial Expressions for On-Chip Interconnect Capacitance.

Atsushi Kurokawa, Masanori Hashimoto, Akira Kasebe, Zhangcai Huang, Yun Yang, Yasuaki Inoue, Ryosuke Inagaki, Hiroo Masuda

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005

Design Guidelines and Process Quality Improvement for Treatment of Device Variations in an Lsi Chip.

Masakazu Aoki, Shin-ichi Ohkawa, Hiroo Masuda

IEICE Trans. Electron., 2005

Capacitance and Yield Evaluations Using a 90-nm Process Technology Based on the Dense Power-Ground Interconnect Architecture.

Atsushi Kurokawa, Masaharu Yamamoto, Nobuto Ono, Tetsuro Kage, Yasuaki Inoue, Hiroo Masuda

Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Dummy Filling Methods for Reducing Interconnect Capacitance and Number of Fills.

Atsushi Kurokawa, Toshiki Kanamoto, Tetsuya Ibe, Akira Kasebe, Wei Fong Chang, Tetsuro Kage, Yasuaki Inoue, Hiroo Masuda

Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Approach for physical design in sub-100 nm era.

Hiroo Masuda, Shin-ichi Ohkawa, Masakazu Aoki

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Challenge: variability characterization and modeling for 65- to 90-nm processes.

Hiroo Masuda, Shin-ichi Ohkawa, Atsushi Kurokawa, Masakazu Aoki

Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

2004

Efficient capacitance extraction method for interconnects with dummy fills.

Atsushi Kurokawa, Toshiki Kanamoto, Akira Kasebe, Yasuaki Inoue, Hiroo Masuda

Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

Large-scale linear circuit simulation with an inversed inductance matrix.

Chieki Mizuta, Jiro Iwai, Ken Machida, Tetsuro Kage, Hiroo Masuda

Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

DEPOGIT: dense power-ground interconnect architecture for physical design integrity.

Atsushi Kurokawa, Nobuto Ono, Tetsuro Kage, Hiroo Masuda

Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003

Crosstalk delay analysis of a 0.13-μm node test chip and precise gate-level simulation technology.

Yasuhiko Sasaki, Mitsumasa Sato, Masaru Kuramoto, Fujio Kikuchi, Tsutomu Kawashima, Hiroo Masuda, Kazuo Yano

IEEE J. Solid State Circuits, 2003

Approximation Formula Approach for the Efficient Extraction of On-Chip Mutual Inductances.

Atsushi Kurokawa, Takashi Sato, Hiroo Masuda

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003

Fast On-Chip Inductance Extraction of VLSI Including Angled Interconnects.

Atsushi Kurokawa, Kotaro Hachiya, Takashi Sato, Kazuya Tokumasu, Hiroo Masuda

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003

Design and Measurement of an Inductance-Oscillator for Analyzing Inductance Impact on On-Chip Interconnect Delay.

Takashi Sato, Hiroo Masuda

Proceedings of the 4th International Symposium on Quality of Electronic Design (ISQED 2003), 2003

Approximate formulae approach for efficient inductance extraction.

Atsushi Kurokawa, Takashi Sato, Hiroo Masuda

Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

1998

TCAD/DA for MPU and ASIC Development.

Hiroo Masuda, Katsumi Tsuneno, Hisako Sato, Kazutaka Mori

Proceedings of the ASP-DAC '98, 1998

1991

A submicrometer MOS transistor I-V model for circuit simulation.

Hiroo Masuda, Jun'ichi Mano, Ryuichi Ikematsu, Hitoshi Sugihara, Yukio Aoki

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991

1988

MOSTSM: a physically based charge conservative MOSFET model.

Hiroo Masuda, Yukio Aoki, Jun'ichi Mano, Osamu Yamashiro

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988

1987

A Two-Dimensional Integrated Process Simulator: SPIRIT-I.

Masanori Ohgo, Yasuko Takano, Akemi Moniwa, Shuichi Yamamoto, Yoshio Sakai, Hiroo Masuda, Hideo Sunami

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1987

A New Design-Centering Methodology for VLSI Device Development.

Yukio Aoki, Hiroo Masuda, Shozo Shimada, Shoji Sato

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1987

1985

Three-Dimensional Device Simulator CADDETH with Highly Convergent Matrix Solution Algorithms.

Toru Toyabe, Hiroo Masuda, Yukio Aoki, Hiroko Shukuri, Takaaki Hagiwara

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1985