Keiichi Yoshida

According to our database, Keiichi Yoshida authored at least 4 papers between 1999 and 2006.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2006

A 130-nm CMOS 95-mm² 1-Gb Multilevel AG-AND-Type Flash Memory with 10-MB/s Programming Throughput.

Hideaki Kurata, Shunichi Saeki, Takashi Kobayashi, Yoshitaka Sasago, Tsuyoshi Arigane, Keiichi Yoshida, Yoshinori Takase, Takayuki Yoshitake, Osamu Tsuchiya, Yoshinori Ikeda, Shunichi Narumi, Michitaro Kanamitsu, Kazuto Izawa, Kazunori Furusawa

IEICE Trans. Electron., 2006

2003

Word Sense Disambiguation Using Pairwise Alignment.

Koichi Yamashita, Keiichi Yoshida, Yukihiro Itoh

Proceedings of the ACL 2003, 2003

1999

A 256-Mb multilevel flash memory with 2-MB/s program rate for mass storage applications.

Atsushi Nozoe, Hiroaki Kotani, Tetsuya Tsujikawa, Keiichi Yoshida, Kazunori Furusawa, Masataka Kato, Toshiaki Nishimoto, Hitoshi Kume, Hideaki Kurata, Naoki Miyamoto, Shoji Kubono, Michitaro Kanamitsu, Kenji Koda, Takeshi Nakayama, Yasuhiro Kouro, Akira Hosogane, Natsuo Ajika, Kiyoteru Kobayashi

IEEE J. Solid State Circuits, 1999

Designing and Implementing a Dialogue Agent Based on Layered Architecture.

Masaya Masuda, Noriaki Izumi, Keiichi Yoshida

Proceedings of the 17th IASTED International Conference on Applied Informatics, 1999