Osamu Tsuchiya

According to our database, Osamu Tsuchiya authored at least 3 papers between 2006 and 2007.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2007

Random Telegraph Signal in Flash Memory: Its Impact on Scaling of Multilevel Flash Memory Beyond the 90-nm Node.

Hideaki Kurata, Kazuo Otsuga, Akira Kotabe, Shinya Kajiyama, Taro Osabe, Yoshitaka Sasago, Shunichi Narumi, Kenji Tokami, Shiro Kamohara, Osamu Tsuchiya

IEEE J. Solid State Circuits, 2007

A 126 mm² 4-Gb Multilevel AG-AND Flash Memory with Inversion-Layer-Bit-Line Technology.

Hideaki Kurata, Satoshi Noda, Yoshitaka Sasago, Kazuo Otsuga, Tsuyoshi Arigane, Tetsufumi Kawamura, Takashi Kobayashi, Hitoshi Kume, Kazuki Homma, Teruhiko Ito, Yoshinori Sakamoto, Masahiro Shimizu, Yoshinori Ikeda, Osamu Tsuchiya, Kazunori Furusawa

IEICE Trans. Electron., 2007

2006

A 130-nm CMOS 95-mm² 1-Gb Multilevel AG-AND-Type Flash Memory with 10-MB/s Programming Throughput.

Hideaki Kurata, Shunichi Saeki, Takashi Kobayashi, Yoshitaka Sasago, Tsuyoshi Arigane, Keiichi Yoshida, Yoshinori Takase, Takayuki Yoshitake, Osamu Tsuchiya, Yoshinori Ikeda, Shunichi Narumi, Michitaro Kanamitsu, Kazuto Izawa, Kazunori Furusawa

IEICE Trans. Electron., 2006