Hitoshi Kume

According to our database, Hitoshi Kume authored at least 5 papers between 1991 and 2007.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2007

A 126 mm² 4-Gb Multilevel AG-AND Flash Memory with Inversion-Layer-Bit-Line Technology.

Hideaki Kurata, Satoshi Noda, Yoshitaka Sasago, Kazuo Otsuga, Tsuyoshi Arigane, Tetsufumi Kawamura, Takashi Kobayashi, Hitoshi Kume, Kazuki Homma, Teruhiko Ito, Yoshinori Sakamoto, Masahiro Shimizu, Yoshinori Ikeda, Osamu Tsuchiya, Kazunori Furusawa

IEICE Trans. Electron., 2007

1999

A 256-Mb multilevel flash memory with 2-MB/s program rate for mass storage applications.

Atsushi Nozoe, Hiroaki Kotani, Tetsuya Tsujikawa, Keiichi Yoshida, Kazunori Furusawa, Masataka Kato, Toshiaki Nishimoto, Hitoshi Kume, Hideaki Kurata, Naoki Miyamoto, Shoji Kubono, Michitaro Kanamitsu, Kenji Koda, Takeshi Nakayama, Yasuhiro Kouro, Akira Hosogane, Natsuo Ajika, Kiyoteru Kobayashi

IEEE J. Solid State Circuits, 1999

1996

Bit-line clamped sensing multiplex and accurate high voltage generator for quarter-micron flash memories.

Takayuki Kawahara, Takashi Kobayashi, Yusuke Jyouno, Syun-ichi Saeki, Naoki Miyamoto, T. Adachi, Masataka Kato, Akihiko Sato, J. Yugami, Hitoshi Kume, Katsutaka Kimura

IEEE J. Solid State Circuits, 1996

1993

A test-path determination method based on define-use chains: Test conditions and program fault overlooks.

Takeshi Nakajo, Ichiro Yamaguchi, Hitoshi Kume

Syst. Comput. Jpn., 1993

1991

A Case History Analysis of Software Error Cause-Effect Relationships.

Takeshi Nakajo, Hitoshi Kume

IEEE Trans. Software Eng., 1991