Yoshitaka Sasago

According to our database1, Yoshitaka Sasago authored at least 5 papers between 2005 and 2007.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2007
Random Telegraph Signal in Flash Memory: Its Impact on Scaling of Multilevel Flash Memory Beyond the 90-nm Node.
IEEE J. Solid State Circuits, 2007

Selective-Capacitance Constant-Charge-Injection Programming Scheme for High-Speed Multilevel AG-AND Flash Memories.
IEICE Trans. Electron., 2007

A 126 mm<sup>2</sup> 4-Gb Multilevel AG-AND Flash Memory with Inversion-Layer-Bit-Line Technology.
IEICE Trans. Electron., 2007

2006
A 130-nm CMOS 95-mm<sup>2</sup> 1-Gb Multilevel AG-AND-Type Flash Memory with 10-MB/s Programming Throughput.
IEICE Trans. Electron., 2006

2005
Constant-charge-injection programming: a novel high-speed programming method for multilevel flash memories.
IEEE J. Solid State Circuits, 2005


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