Unni Narayanan

According to our database1, Unni Narayanan authored at least 11 papers between 1997 and 2003.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

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Bibliography

2003
Noise-aware interconnect power optimization in domino logic synthesis.
IEEE Trans. Very Large Scale Integr. Syst., 2003

2002
Enhanced bus invert encodings for low-power.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

2000
Decomposition of Bus-Invert Coding for Low-Power I/O.
J. Circuits Syst. Comput., 2000

Noise-aware power optimization for on-chip interconnect.
Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000

Domino logic synthesis minimizing crosstalk.
Proceedings of the 37th Conference on Design Automation, 2000

1999
Characterizing Individual Gate Power Sensitivity in Low Power Design.
Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

Automated Phase Assignment for the Synthesis of Low Power Domino Circuits.
Proceedings of the 36th Conference on Design Automation, 1999

1998
Algorithmic Techniques for Logic Synthesis of Low Power VLSI Circuits
PhD thesis, 1998

Low power logic synthesis under a general delay model.
Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998

1997
Low power multiplexer decomposition.
Proceedings of the 1997 International Symposium on Low Power Electronics and Design, 1997

Low power logic synthesis for XOR based circuits.
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997


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