Kosuke Furuichi

According to our database, Kosuke Furuichi authored at least 5 papers between 2016 and 2018.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2018

A 25-Gb/s 13 mW clock and data recovery using C²MOS D-flip-flop in 65-nm CMOS.

Ryosuke Noguchi, Kosuke Furuichi, Hiromu Uemura, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine, Hiroaki Katsurai, Shinsuke Nakano, Hideyuki Nosaka

Proceedings of the 2018 International Symposium on VLSI Design, 2018

2017

25-Gb/s clock and data recovery IC using latch-load combined with CML buffer circuit for delay generation with 65-nm CMOS.

Tomonori Tanaka, Kosuke Furuichi, Hiromu Uemura, Ryosuke Noguchi, Natsuyuki Koda, Koki Arauchi, Daichi Omoto, Hiromi Inaba, Keiji Kishine, Shinsuke Nakano, Masafumi Nogawa, Hideyuki Nosaka

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2016

Proposal for sensitive frequency demodulator for 10-Gb/s transmission labeling signal system.

Natsuyuki Koda, Kosuke Furuichi, Hiromu Uemura, Hiromi Inaba, Keiji Kishine

Proceedings of the International SoC Design Conference, 2016

36-Gb/s CDR IC using simple passive loop filter combined with passive load in phase detector.

Keiji Kishine, Hiroshi Inoue, Kosuke Furuichi, Natsuyuki Koda, Hiromu Uemura, Hiromi Inaba, Makoto Nakamura, Akira Tsuchiya

Proceedings of the International SoC Design Conference, 2016

Design of high-linearity delay detection circuit for 10-Gb/s communication system in 65-nm CMOS.

Kosuke Furuichi, Hiromu Uemura, Natsuyuki Koda, Hiromi Inaba, Keiji Kishine

Proceedings of the International SoC Design Conference, 2016