Toshiyuki Inoue
Orcid: 0000-0002-6621-1412
According to our database1,
Toshiyuki Inoue
authored at least 35 papers
between 2014 and 2024.
Collaborative distances:
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Bibliography
2024
Proceedings of the International Conference on Electronics, Information, and Communication, 2024
2023
Low-power and small-area 4-ch 25-Gb/s transimpedance amplifiers in 65-nm CMOS process.
IEICE Electron. Express, 2023
10Gb/s burst-mode driver circuit with on-chip bias switch for in-Vehicle optical networks.
IEICE Electron. Express, 2023
4-ch 25-Gb/s Small and Low-power VCSEL Driver Circuit with Unbalanced CML in 65-nm CMOS.
Proceedings of the 20th International SoC Design Conference, 2023
Proceedings of the 30th IEEE International Conference on Electronics, Circuits and Systems, 2023
Proceedings of the 15th IEEE International Conference on ASIC, 2023
2022
A Small-Area Integration of Optical Receiver Using Multi-Layer Inductors and Capacitor-Under-Pad.
Proceedings of the 65th IEEE International Midwest Symposium on Circuits and Systems, 2022
Proceedings of the 65th IEEE International Midwest Symposium on Circuits and Systems, 2022
Smart Computational Resource Distribution System with Automatic Classification Interface for CPS.
Proceedings of the 19th International SoC Design Conference, 2022
Memory-Access Optimization for Acceleration and Power Saving of FPGA-Based Image Processing.
Proceedings of the 19th International SoC Design Conference, 2022
A Method for Implementing LSTM-Based Multiple-People Identification System for Non-Contact Health Monitoring on Small-Scale FPGA.
Proceedings of the 19th International SoC Design Conference, 2022
Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022
A Fine-Tuning Phase Shifter with Vector Synthesizer Using 65-nm CMOS for Beamforming in 24-GHz Band.
Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022
Process Acceleration for HEVC Using Parallel Characteristics Calculation and Pixel Array Conversion.
Proceedings of the International Conference on Electronics, Information, and Communication, 2022
Capacitor Under Pad for Small Area Integration of High-Speed Signal-to-Differential Amplifier.
Proceedings of the International Conference on Electronics, Information, and Communication, 2022
A preamplifier circuit with offset-voltage control technique for 50-Gb/s CMOS PAM4 receiver.
Proceedings of the International Conference on Electronics, Information, and Communication, 2022
Method of Estimating Positions for Multiple People in Non-Contact Vital Signs Monitoring Systems.
Proceedings of the International Conference on Electronics, Information, and Communication, 2022
Supply-Variation-Tolerant Transimpedance Amplifier Using Non-Inverting Amplifier in 180-nm CMOS.
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022
2021
A Burst-Mode TIA with Adaptive Response and Stable Operation for in-Vehicle Optical Networks.
Proceedings of the 28th IEEE International Conference on Electronics, 2021
Implementation of Low-Energy LSTM with Parallel and Pipelined Algorithm in Small-Scale FPGA.
Proceedings of the International Conference on Electronics, Information, and Communication, 2021
Proceedings of the International Conference on Electronics, Information, and Communication, 2021
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021
2020
Proceedings of the International SoC Design Conference, 2020
2019
Impact of On-Chip Inductor and Power-Delivery-Network Stacking on Signal and Power Integrity.
IEICE Trans. Electron., 2019
Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019
Proceedings of the 2019 International SoC Design Conference, 2019
Proceedings of the 2019 International SoC Design Conference, 2019
Proceedings of the 2019 International SoC Design Conference, 2019
2018
A 25-Gb/s 13 mW clock and data recovery using C<sup>2</sup>MOS D-flip-flop in 65-nm CMOS.
Proceedings of the 2018 International Symposium on VLSI Design, 2018
Low-Power and High-Linearity Inductorless Low-Noise Amplifiers with Active-Shunt-Feedback in 65-nm CMOS Technology.
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018
A 25-Gb/s Low-Power Clock and Data Recovery with an Active-Stabilizing CML-CMOS Conversion.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018
2017
Proceedings of the International SoC Design Conference, 2017
Design method for inductorless low-noise amplifiers with active shunt-feedback in 65-nm CMOS.
Proceedings of the International SoC Design Conference, 2017
Proceedings of the International SoC Design Conference, 2017
2014
Fabrication of MgO: LiNbO<sub>3</sub> Domain Inverted Structures with Short Period and Application to Electro-Optic Bragg Deflection Modulator.
IEICE Trans. Electron., 2014