Natsuyuki Koda

According to our database1, Natsuyuki Koda authored at least 5 papers between 2016 and 2017.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2017
FPGA-based transceiver circuit for labeling signal transmission system.
Proceedings of the International SoC Design Conference, 2017

25-Gb/s clock and data recovery IC using latch-load combined with CML buffer circuit for delay generation with 65-nm CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2016
Proposal for sensitive frequency demodulator for 10-Gb/s transmission labeling signal system.
Proceedings of the International SoC Design Conference, 2016

36-Gb/s CDR IC using simple passive loop filter combined with passive load in phase detector.
Proceedings of the International SoC Design Conference, 2016

Design of high-linearity delay detection circuit for 10-Gb/s communication system in 65-nm CMOS.
Proceedings of the International SoC Design Conference, 2016


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