Shinsuke Nakano

According to our database1, Shinsuke Nakano authored at least 8 papers between 2014 and 2019.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2019
A wideband current-reuse-RGC TIA circuit with low-power consumption.
IEICE Electron. Express, 2019

2018
A 25-Gb/s 13 mW clock and data recovery using C<sup>2</sup>MOS D-flip-flop in 65-nm CMOS.
Proceedings of the 2018 International Symposium on VLSI Design, 2018

A 137-mW, 4 ch × 25-Gbps Low-Power Compact Transmitter Flip-Chip-Bonded 1.3-μm LD-Array-on-Si.
Proceedings of the Optical Fiber Communications Conference and Exposition, 2018

Ultra-Low Power Dissipation (<2.4 W) Coherent InP Modulator Module with CMOS Driver IC.
Proceedings of the European Conference on Optical Communication, 2018

2017
25-Gb/s clock and data recovery IC using latch-load combined with CML buffer circuit for delay generation with 65-nm CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

A 180-mW Linear MZM Driver in CMOS for Single-Carrier 400-Gb/s Coherent Optical Transmitter.
Proceedings of the European Conference on Optical Communication, 2017

2015
A 25-Gb/s 480-mW CMOS modulator driver using area-efficient 3D inductor peaking.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015

2014
20.1-mW 8-Gbps UWB-IR millimeter-wave transmitter using an OOK pulse modulator based on CMOS inverters.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014


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