Tanja Harbaum

Orcid: 0000-0001-7310-567X

According to our database1, Tanja Harbaum authored at least 25 papers between 2013 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
CNNParted: An open source framework for efficient Convolutional Neural Network inference partitioning in embedded systems.
Comput. Networks, June, 2023

Approximate Accelerators: A Case Study using Runtime Reconfigurable Processors.
Proceedings of the 36th IEEE International System-on-Chip Conference, 2023

Leveraging Mixed-Precision CNN Inference for Increased Robustness and Energy Efficiency.
Proceedings of the 36th IEEE International System-on-Chip Conference, 2023

Automated Replacement of State-Holding Flip-Flops to Enable Non-Volatile Checkpointing.
Proceedings of the IEEE Nordic Circuits and Systems Conference, 2023

Low-latency inter-domain communication on the Xen hypervisor.
Proceedings of the 16th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2023

Reinforcement Learning Enabled Multi-Layered NoC for Mixed Criticality Systems.
Proceedings of the 16th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2023

DREAM: Distributed Reinforcement Learning Enabled Adaptive Mixed-Critical NoC.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2023

Design Space Exploration on Efficient and Accurate Human Pose Estimation from Sparse IMU-Sensing.
IROS, 2023

EFFECT: An End-to-End Framework for Evaluating Strategies for Parallel AI Anomaly Detection.
Proceedings of the International Neural Network Society Workshop on Deep Learning Innovations and Applications, 2023

Non-Intrusive Runtime Monitoring for Manycore Prototypes.
Proceedings of the DroneSE and RAPIDO: System Engineering for constrained embedded systems, 2023

An Analytical Model of Configurable Systolic Arrays to find the Best-Fitting Accelerator for a given DNN Workload.
Proceedings of the DroneSE and RAPIDO: System Engineering for constrained embedded systems, 2023

SiFI-AI: A Fast and Flexible RTL Fault Simulation Framework Tailored for AI Models and Accelerators.
Proceedings of the Great Lakes Symposium on VLSI 2023, 2023

Mitigating Masking in Automotive Communication Systems: Modeling and Hardware Generation.
Proceedings of the 26th Euromicro Conference on Digital System Design, 2023

ATLAS: An Approximate Time-Series LSTM Accelerator for Low-Power IoT Applications.
Proceedings of the 26th Euromicro Conference on Digital System Design, 2023

The ZuSE-KI-Mobil AI Accelerator SoC: Overview and a Functional Safety Perspective.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

A Hardware-Centric Approach to Increase and Prune Regular Activation Sparsity in CNNs.
Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023

2022
Runtime Adaptive Cache Checkpointing for RISC Multi-Core Processors.
Proceedings of the 35th IEEE International System-on-Chip Conference, 2022

Automated Search for Deep Neural Network Inference Partitioning on Embedded FPGA.
Proceedings of the Machine Learning and Principles and Practice of Knowledge Discovery in Databases, 2022

Hardware-aware Workload Distribution for AI-based Online Handwriting Recognition in a Sensor Pen.
Proceedings of the 11th Mediterranean Conference on Embedded Computing, 2022

Hardware-aware Partitioning of Convolutional Neural Network Inference for Embedded AI Applications.
Proceedings of the 18th International Conference on Distributed Computing in Sensor Systems, 2022

2019
A Hardware Perspective on the ChaCha Ciphers: Scalable Chacha8/12/20 Implementations Ranging from 476 Slices to Bitrates of 175 Gbit/s.
Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019

2018
A Content - Adapted FPGA Memory Architecture with Pattern Recognition Capability and Interval Compressing Technique.
Proceedings of the 31st IEEE International System-on-Chip Conference, 2018

2017
Auto-SI: An adaptive reconfigurable processor with run-time loop detection and acceleration.
Proceedings of the 30th IEEE International System-on-Chip Conference, 2017

2016
A Content Adapted FPGA Memory Architecture with Pattern Recognition Capability for L1 Track Triggering in the LHC Environment.
Proceedings of the 24th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2016

2013
LImbiC: An adaptable architecture description language model for developing an application-specific image processor.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013


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