Amit Ranjan Trivedi
Orcid: 0000-0001-5436-7922
According to our database1,
Amit Ranjan Trivedi
authored at least 64 papers
between 2007 and 2024.
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Bibliography
2024
Echoes of Socratic Doubt: Embracing Uncertainty in Calibrated Evidential Reinforcement Learning.
CoRR, 2024
Navigating the Unknown: Uncertainty-Aware Compute-in-Memory Autonomy of Edge Robotics.
CoRR, 2024
Towards Model-Size Agnostic, Compute-Free, Memorization-based Inference of Deep Learning.
Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024
2023
IEEE Trans. Circuits Syst. I Regul. Pap., February, 2023
Containing Analog Data Deluge at Edge through Frequency-Domain Compression in Collaborative Compute-in-Memory Networks.
CoRR, 2023
STARNet: Sensor Trustworthiness and Anomaly Recognition via Approximated Likelihood Regret for Robust Edge Autonomy.
CoRR, 2023
Mutual Information-calibrated Conformal Feature Fusion for Uncertainty-Aware Multimodal 3D Object Detection at the Edge.
CoRR, 2023
ADC/DAC-Free Analog Acceleration of Deep Neural Networks with Frequency Transformation.
CoRR, 2023
Towards Model-Size Agnostic, Compute-Free, Memorization-based Inference of Deep Learning.
CoRR, 2023
Unifying Intrinsically-Operated Physically Unclonable Function and Random Number Generation in Analog Circuits: A Case Study on Successive Approximation ADC.
Proceedings of the 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems, 2023
Exploiting Programmable Dipole Interaction in Straintronic Nanomagnet Chains for Ising Problems.
Proceedings of the 24th International Symposium on Quality Electronic Design, 2023
Readout IC with 40 MSPS in-pixel ADC for future vertex detector upgrades of Large Hadron Collider.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
Proceedings of the International Joint Conference on Neural Networks, 2023
Robust Monocular Localization of Drones by Adapting Domain Maps to Depth Prediction Inaccuracies.
Proceedings of the IEEE International Conference on Acoustics, 2023
Memory-Immersed Collaborative Digitization for Area-Efficient Compute-in-Memory Deep Learning.
Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023
2022
Ultralow-Power Localization of Insect-Scale Drones: Interplay of Probabilistic Filtering and Compute-in-Memory.
IEEE Trans. Very Large Scale Integr. Syst., 2022
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
IEEE Internet Things J., 2022
IEEE Access, 2022
Non van-Neumann Anomaly Detection in Multi-Channel Time-Series using Charge Trap Transistor Crossbars.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022
Analog-Domain Time-Series Moment Extraction for Low Power Predictive Maintenance Analytics.
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022
2021
IEEE Trans. Very Large Scale Integr. Syst., 2021
MF-Net: Compute-In-Memory SRAM for Multibit Precision Inference Using Memory-Immersed Data Conversion and Multiplication-Free Operators.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
ENOS: Energy-Aware Network Operator Search for Hybrid Digital and Compute-in-Memory DNN Accelerators.
CoRR, 2021
Compute-in-Memory Upside Down: A Learning Operator Co-Design Perspective for Scalability.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
2020
Low Power Unsupervised Anomaly Detection by Nonparametric Modeling of Sensor Statistics.
IEEE Trans. Very Large Scale Integr. Syst., 2020
Low Power Speaker Identification by Integrated Clustering and Gaussian Mixture Model Scoring.
IEEE Embed. Syst. Lett., 2020
Low Latency CMOS Hardware Acceleration for Fully Connected Layers in Deep Neural Networks.
CoRR, 2020
Low Power Unsupervised Anomaly Detection by Non-Parametric Modeling of Sensor Statistics.
CoRR, 2020
MC<sup>2</sup>RAM: Markov Chain Monte Carlo Sampling in SRAM for Fast Bayesian Inference.
CoRR, 2020
Energy-Efficient Acceleration of Deep Neural Networks on Realtime-Constrained Embedded Edge Devices.
IEEE Access, 2020
Non-parametric Statistical Density Function Synthesizer and Monte Carlo Sampler in CMOS.
Proceedings of the 33rd International Conference on VLSI Design and 19th International Conference on Embedded Systems, 2020
Proceedings of the 21st International Symposium on Quality Electronic Design, 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Supported-BinaryNet: Bitcell Array-Based Weight Supports for Dynamic Accuracy-Energy Trade-Offs in SRAM-Based Binarized Neural Network.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
2019
An Intrinsic and Database-Free Authentication by Exploiting Process Variation in Back-End Capacitors.
IEEE Trans. Very Large Scale Integr. Syst., 2019
Supported-BinaryNet: Bitcell Array-based Weight Supports for Dynamic Accuracy-Latency Trade-offs in SRAM-based Binarized Neural Network.
CoRR, 2019
Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019
Self-Organizing Maps-Based Flexible and High-Speed Packet Classification in Software Defined Networking.
Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019
Proceedings of the Fifth Workshop on Energy Efficient Machine Learning and Cognitive Computing, 2019
Proceedings of the IEEE Symposium in Low-Power and High-Speed Chips, 2019
2018
Intrinsic and Database-free Watermarking in ICs by Exploiting Process and Design Dependent Variability in Metal-Oxide-Metal Capacitances.
Proceedings of the International Symposium on Low Power Electronics and Design, 2018
Proceedings of the 55th Annual Design Automation Conference, 2018
2017
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017
A solitary protection measure against scan chain, fault injection, and power analysis attacks on AES.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017
2016
Impact of Heterogeneous Technology Integration on the Power, Performance, and Quality of a 3D Image Sensor.
IEEE Trans. Multi Scale Comput. Syst., 2016
IEEE J. Emerg. Sel. Topics Circuits Syst., 2016
CoRR, 2016
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016
Gate/source-overlapped heterojunction Tunnel FET-based LAMSTAR neural network and its Application to EEG Signal Classification.
Proceedings of the 2016 International Joint Conference on Neural Networks, 2016
2015
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015
2014
IEEE Trans. Circuits Syst. II Express Briefs, 2014
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
2013
Exploring tunnel-FET for ultra low power analog applications: a case study on operational transconductance amplifier.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013
Proceedings of the Advances In Robotics 2013, 2013
2012
On the parametric failures of SRAM in a 3D-die stack considering tier-to-tier supply cross-talk.
Proceedings of the 30th IEEE VLSI Test Symposium, 2012
Self-adaptive power gating with test circuit for on-line characterization of energy inflection activity.
Proceedings of the 30th IEEE VLSI Test Symposium, 2012
2010
Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010
2007
Switching voltage, dynamic power dissipation and on-to-off conductance ratio of a spin field effect transistor.
IET Circuits Devices Syst., 2007