Kwangok Jeong

According to our database1, Kwangok Jeong authored at least 19 papers between 2008 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2022
Hardware Performance Monitoring Methodology at Near-Threshold Computing and Advanced Technology Nodes: From Design to Postsilicon.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

2020
SRAM on-chip monitoring methodology for high yield and energy efficient memory operation at near threshold voltage.
Integr., 2020

Synthesis of Hardware Performance Monitoring and Prediction Flow Adapting to Near-Threshold Computing and Advanced Process Nodes.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

2019
SRAM On-Chip Monitoring Methodology for Energy Efficient Memory Operation at Near Threshold Voltage.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

2012
MAPG: Memory access power gating.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011
Toward PDN resource estimation: A law of general power density.
Proceedings of the 2011 International Workshop on System Level Interconnect Prediction, 2011

Stability and scalability in global routing.
Proceedings of the 2011 International Workshop on System Level Interconnect Prediction, 2011

2010
Dose Map and Placement Co-Optimization for Improved Timing Yield and Leakage Power.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Timing Yield-Aware Color Reassignment and Detailed Placement Perturbation for Bimodal CD Distribution in Double Patterning Lithography.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Accurate Machine-Learning-Based On-Chip Router Modeling.
IEEE Embed. Syst. Lett., 2010

Assessing chip-level impact of double patterning lithography.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

Toward effective utilization of timing exceptions in design optimization.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

Methodology from chaos in IC implementation.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

2009
Is overlay error more important than interconnect variations in double patterning?
Proceedings of the 11th International Workshop on System-Level Interconnect Prediction (SLIP 2009), 2009

Revisiting the linear programming framework for leakage power vs. performance optimization.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

Timing yield-aware color reassignment and detailed placement perturbation for double patterning lithography.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

Timing analysis and optimization implications of bimodal CD distribution in double patterning lithography.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008
Quantified Impacts of Guardband Reduction on Design Process Outcomes.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

Dose map and placement co-optimization for timing yield enhancement and leakage power reduction.
Proceedings of the 45th Design Automation Conference, 2008


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