Kambiz Samadi

According to our database1, Kambiz Samadi authored at least 40 papers between 2006 and 2019.

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Bibliography

2019
Mixed-Signal Charge-Domain Acceleration of Deep Neural networks through Interleaved Bit-Partitioned Arithmetic.
CoRR, 2019

GAN-CTS: A Generative Adversarial Framework for Clock Tree Prediction and Optimization.
Proceedings of the International Conference on Computer-Aided Design, 2019

Power Delivery Pathfinding for Emerging Die-to-Wafer Integration Technology.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018
GANAX: A Unified MIMD-SIMD Acceleration for Generative Adversarial Networks.
CoRR, 2018

GANAX: A Unified MIMD-SIMD Acceleration for Generative Adversarial Networks.
Proceedings of the 45th ACM/IEEE Annual International Symposium on Computer Architecture, 2018

SnaPEA: Predictive Early Activation for Reducing Computation in Deep Convolutional Neural Networks.
Proceedings of the 45th ACM/IEEE Annual International Symposium on Computer Architecture, 2018

FlexiGAN: An End-to-End Solution for FPGA Acceleration of Generative Adversarial Networks.
Proceedings of the 26th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2018

2017
A Single-Tier Virtual Queuing Memory Controller Architecture for Heterogeneous MPSoCs.
ACM Trans. Design Autom. Electr. Syst., 2017

Full Chip Impact Study of Power Delivery Network Designs in Gate-Level Monolithic 3-D ICs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2017

Tier Degradation of Monolithic 3-D ICs: A Power Performance Study at Different Technology Nodes.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2017

Shrunk-2-D: A Physical Design Methodology to Build Commercial-Quality Monolithic 3-D ICs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2017

2016
Adaptive Regression-Based Thermal Modeling and Optimization for Monolithic 3-D ICs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2016

BEOL stack-aware routability prediction from placement using data mining techniques.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016

Single-tier virtual queuing: an efficacious memory controller architecture for MPSoCs with multiple realtime cores.
Proceedings of the 53rd Annual Design Automation Conference, 2016

2015
Placement-Driven Partitioning for Congestion Mitigation in Monolithic 3D IC Designs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2015

Multi-product floorplan and uncore design framework for chip multiprocessors.
Proceedings of the 2015 ACM/IEEE International Workshop on System Level Interconnect Prediction, 2015

3D VLSI: A Scalable Integration Beyond 2D.
Proceedings of the 2015 Symposium on International Symposium on Physical Design, ISPD 2015, Monterey, CA, USA, March 29, 2015

Tier-partitioning for power delivery vs cooling tradeoff in 3D VLSI for mobile applications.
Proceedings of the 52nd Annual Design Automation Conference, 2015

3DIC benefit estimation and implementation guidance from 2DIC implementation.
Proceedings of the 52nd Annual Design Automation Conference, 2015

2014
Design and CAD methodologies for low power gate-level monolithic 3D ICs.
Proceedings of the International Symposium on Low Power Electronics and Design, 2014

Full chip impact study of power delivery network designs in monolithic 3D ICs.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

Fast and Accurate Thermal Modeling and Optimization for Monolithic 3D ICs.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Power-Performance Study of Block-Level Monolithic 3D-ICs Considering Inter-Tier Performance Variations.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Thermal implications of mobile 3D-ICs.
Proceedings of the 2014 International 3D Systems Integration Conference, 2014

2013
High-density integration of functional modules using monolithic 3D-IC technology.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

Test-TSV estimation during 3D-IC partitioning.
Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013

2012
ORION 2.0: A Power-Area Simulator for Interconnection Networks.
IEEE Trans. VLSI Syst., 2012

2010
Accurate Predictive Interconnect Modeling for System-Level Design.
IEEE Trans. VLSI Syst., 2010

Accurate Machine-Learning-Based On-Chip Router Modeling.
Embedded Systems Letters, 2010

Worst-case performance prediction under supply voltage and temperature variation.
Proceedings of the International Workshop on System Level Interconnect Prediction Workshop, 2010

Efficient trace-driven metaheuristics for optimization of networks-on-chip configurations.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

Trace-driven optimization of networks-on-chip configurations.
Proceedings of the 47th Design Automation Conference, 2010

Improved on-chip router analytical power and area modeling.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009
ORION 2.0: A fast and accurate NoC power and area model for early-stage design space exploration.
Proceedings of the Design, Automation and Test in Europe, 2009

2008
CMP Fill Synthesis.
Proceedings of the Handbook of Algorithms for Physical Design Automation., 2008

CMP Fill Synthesis: A Survey of Recent Studies.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2008

Quantified Impacts of Guardband Reduction on Design Process Outcomes.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

Interconnect modeling for improved system-level design optimization.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2006
Wafer Topography-Aware Optical Proximity Correction.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

Study of Floating Fill Impact on Interconnect Capacitance.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006


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