Jingwei Lu

Orcid: 0000-0001-5789-3522

According to our database1, Jingwei Lu authored at least 35 papers between 2009 and 2024.

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Bibliography

2024
An Identity-Based Encryption with Equality Test scheme for healthcare social apps.
Comput. Stand. Interfaces, January, 2024

2023
Continuous-Time Stochastic Policy Iteration of Adaptive Dynamic Programming.
IEEE Trans. Syst. Man Cybern. Syst., October, 2023

DeFACT in ManuVerse for Parallel Manufacturing: Foundation Models and Parallel Workers in Smart Factories.
IEEE Trans. Syst. Man Cybern. Syst., April, 2023

Metaverses-Based Parallel Oil Fields in CPSS: A Framework and Methodology.
IEEE Trans. Syst. Man Cybern. Syst., April, 2023

Event-Triggered Deep Reinforcement Learning Using Parallel Control: A Case Study in Autonomous Driving.
IEEE Trans. Intell. Veh., April, 2023

Event-Triggered Near-Optimal Control for Unknown Discrete-Time Nonlinear Systems Using Parallel Control.
IEEE Trans. Cybern., March, 2023

Certificateless Public Key Authenticated Encryption with Keyword Search Achieving Stronger Security.
Inf., 2023

2022
Discrete-Time Self-Learning Parallel Control.
IEEE Trans. Syst. Man Cybern. Syst., 2022

Event-Triggered Optimal Parallel Tracking Control for Discrete-Time Nonlinear Systems.
IEEE Trans. Syst. Man Cybern. Syst., 2022

Neural Dynamics for Computing Perturbed Nonlinear Equations Applied to ACP-Based Lower Limb Motion Intention Recognition.
IEEE Trans. Syst. Man Cybern. Syst., 2022

Event-Triggered Near-Optimal Control of Discrete-Time Constrained Nonlinear Systems With Application to a Boiler-Turbine System.
IEEE Trans. Ind. Informatics, 2022

Event-triggered optimal control for discrete-time multi-player non-zero-sum games using parallel control.
Inf. Sci., 2022

A New Neuro-Optimal Nonlinear Tracking Control Method via Integral Reinforcement Learning with Applications to Nuclear Systems.
Neurocomputing, 2022

Parallel Factories for Smart Industrial Operations: From Big AI Models to Field Foundational Models and Scenarios Engineering.
IEEE CAA J. Autom. Sinica, 2022

2021
Backstepping-Based Parallel Control for Cascaded Nonlinear Systems.
Proceedings of the IEEE 2nd International Conference on Digital Twins and Parallel Intelligence, 2021

2020
Parallel control for optimal tracking via adaptive dynamic programming.
IEEE CAA J. Autom. Sinica, 2020

Dimensionality Reduction Method for 3D-Handwritten Characters Based on Oriented Bounding Boxes.
IEEE Access, 2020

2019
Segmentation of Building Footprints with Xception and IoUloss.
Proceedings of the IEEE International Conference on Multimedia & Expo Workshops, 2019

Text to Image Synthesis Based on Multiple Discrimination.
Proceedings of the Artificial Neural Networks and Machine Learning - ICANN 2019: Image Processing, 2019

2016
ePlace-3D: Electrostatics based Placement for 3D-ICs.
Proceedings of the 2016 on International Symposium on Physical Design, 2016

2015
ePlace: Electrostatics-Based Placement Using Fast Fourier Transform and Nesterov's Method.
ACM Trans. Design Autom. Electr. Syst., 2015

ePlace-MS: Electrostatics-Based Placement for Mixed-Size Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Simulation Algorithms with Exponential Integration for Time-Domain Analysis of Large-Scale Power Delivery Networks.
CoRR, 2015

2014
Analytic VLSI Placement using Electrostatic Analogy.
PhD thesis, 2014

Security of the Internet of Things: perspectives and challenges.
Wirel. Networks, 2014

Worst-case noise area prediciton of on-chip power distribution network.
Proceedings of the ACM/IEEE International Workshop on System Level Interconnect Prediction, 2014

ePlace: Electrostatics Based Placement Using Nesterov's Method.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

2013
LMgr: A low-M emory global router with dynamic topology update and bending-aware optimum path search.
Proceedings of the International Symposium on Quality Electronic Design, 2013

FFTPL: An analytic placement algorithm using fast fourier transform for density equalization.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

2012
Fast Power- and Slew-Aware Gated Clock Tree Synthesis.
IEEE Trans. Very Large Scale Integr. Syst., 2012

A new clock network synthesizer for modern VLSI designs.
Integr., 2012

2011
Stability and scalability in global routing.
Proceedings of the 2011 International Workshop on System Level Interconnect Prediction, 2011

2010
Clock Network Synthesis with Concurrent Gate Insertion.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2010

A dual-MST approach for clock network synthesis.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009
Congestion prediction in early stages of physical design.
ACM Trans. Design Autom. Electr. Syst., 2009


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