Kyung Rok Kim
Orcid: 0000-0003-0124-5520
According to our database1,
Kyung Rok Kim
authored at least 12 papers
between 2003 and 2025.
Collaborative distances:
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Bibliography
2025
CoRR, June, 2025
Ultra-low power and 1.5 bit/cell ternary-SRAM stability modeling for always-on applications.
IEICE Electron. Express, 2025
Proceedings of the Conference on Uncertainty in Artificial Intelligence, 2025
2024
A 28-nm 323 TOPS/mm<sup>2</sup>/b and 2007 TOPS/W/b Ternary Latch Based Sparsity-Aware CIM Macro With Double-Sampling Ternary ADC.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2024
2023
Energy Efficient Ternary Device in 28-nm CMOS Technology with Excellent Short-Channel Effect Immunity and Variation Tolerance Characteristics.
Proceedings of the Device Research Conference, 2023
Proceedings of the Device Research Conference, 2023
2020
IEEE Trans. Circuits Syst. I Regul. Pap., 2020
2017
CMOS-Compatible Ternary Device Platform for Physical Synthesis of Multi-valued Logic Circuits.
Proceedings of the 47th IEEE International Symposium on Multiple-Valued Logic, 2017
Proceedings of the 47th IEEE International Symposium on Multiple-Valued Logic, 2017
2013
IEICE Trans. Electron., 2013
2010
Investigation of source-to-drain capacitance by DIBL effect of silicon nanowire MOSFETs.
IEICE Electron. Express, 2010
2003
Complementary Self-Biased Scheme for the Robust Design of CMOS/SET Hybrid Multi-Valued Logic.
Proceedings of the 33rd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2003), 2003