Ki-Whan Song
According to our database1,
Ki-Whan Song
authored at least 16 papers
between 2001 and 2022.
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Bibliography
2022
Novel Electrical Detection Method for Random Defects on Peripheral Circuits in NAND Flash Memory.
Proceedings of the IEEE International Reliability Physics Symposium, 2022
Electric Field Impact on Lateral Charge Diffusivity in Charge Trapping 3D NAND Flash Memory.
Proceedings of the IEEE International Reliability Physics Symposium, 2022
Proceedings of the International Conference on Electronics, Information, and Communication, 2022
2020
13.1 A 1Tb 4b/cell NAND Flash Memory with tPROG=2ms, tR=110µs and 1.2Gb/s High-Speed IO Rate.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
2019
A 512Gb 3-bit/Cell 3D 6<sup>th</sup>-Generation V-NAND Flash Memory with 82MB/s Write Throughput and 1.2Gb/s Interface.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
2018
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
A flash memory controller for 15μs ultra-low-latency SSD using high-speed 3D NAND flash with 3μs read time.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
2016
IEEE Trans. Very Large Scale Integr. Syst., 2016
2013
Adaptive Multi-Pulse Program Scheme Based on Tunneling Speed Classification for Next Generation Multi-Bit/Cell NAND FLASH.
IEEE J. Solid State Circuits, 2013
2012
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
2011
Microelectron. J., 2011
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
2010
A 31 ns Random Cycle VCAT-Based 4F <sup>2</sup> DRAM With Manufacturability and Enhanced Cell Efficiency.
IEEE J. Solid State Circuits, 2010
2006
A 512-mb DDR3 SDRAM prototype with C<sub>IO</sub> minimization and self-calibration techniques.
IEEE J. Solid State Circuits, 2006
2003
Complementary Self-Biased Scheme for the Robust Design of CMOS/SET Hybrid Multi-Valued Logic.
Proceedings of the 33rd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2003), 2003
2001
A 2.5-V 2.0-Gbyte/s 288-Mb packet-based DRAM with enhanced cell efficiency and noise immunity.
IEEE J. Solid State Circuits, 2001