Lingamneni Avinash

According to our database1, Lingamneni Avinash authored at least 20 papers between 2007 and 2015.

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Bibliography

2015
Leveraging the Error Resilience of Neural Networks for Designing Highly Energy Efficient Accelerators.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Perceptually guided inexact DSP design for power, area efficient hearing aid.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2015

2014
Highly energy-efficient and quality-tunable inexact FFT accelerators.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

Leveraging the error resilience of machine-learning applications for designing highly energy efficient accelerators.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013
Ten Years of Building Broken Chips: The Physics and Engineering of Inexact Computing.
ACM Trans. Embed. Comput. Syst., 2013

Synthesizing Parsimonious Inexact Circuits through Probabilistic Design Techniques.
ACM Trans. Embed. Comput. Syst., 2013

Designing Energy-Efficient Arithmetic Operators Using Inexact Computing.
J. Low Power Electron., 2013

Why design reliable chips when faulty ones are even better.
Proceedings of the ESSCIRC 2013, 2013

Improving energy gains of <i>inexact</i> DSP hardware through <i>reciprocative error compensation</i>.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

2012
What to do about the end of Moore's law, probably!
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Algorithmic methodologies for ultra-efficient inexact architectures for sustaining technology scaling.
Proceedings of the Computing Frontiers Conference, CF'12, 2012

2011
Parsimonious Circuits for Error-Tolerant Applications through Probabilistic Logic Minimization.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2011

Energy parsimonious circuit design through probabilistic pruning.
Proceedings of the Design, Automation and Test in Europe, 2011

2009
Sustaining moore's law in embedded computing through probabilistic and approximate design: retrospects and prospects.
Proceedings of the 2009 International Conference on Compilers, 2009

2008
A Novel Encoding Scheme for Delay and Energy Minimization in VLSI Interconnects with Built-In Error Detection.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008

Highly energy and performance efficient embedded computing through approximately correct arithmetic: a mathematical foundation and preliminary experimental validation.
Proceedings of the 2008 International Conference on Compilers, 2008

2007
Novel Architectures for High-Speed and Low-Power 3-2, 4-2 and 5-2 Compressors.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Novel, High-Speed 16-Digit BCD Adders Conforming to IEEE 754r Format.
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

Novel High-Speed Redundant Binary to Binary converter using Prefix Networks.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Novel architectures for efficient (m, n) parallel counters.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007


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