Logan Rakai

  • University of Calgary, Canada

According to our database1, Logan Rakai authored at least 32 papers between 2006 and 2022.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.



In proceedings 
PhD thesis 


Online presence:

On csauthors.net:


SODA-Stream: SDN Optimization for Enhancing QoE in DASH Streaming.
Proceedings of the 2022 IEEE/IFIP Network Operations and Management Symposium, 2022

Dynamic Cloud Resource Allocation Considering Demand Uncertainty.
IEEE Trans. Cloud Comput., 2021

Eh?Predictor: A Deep Learning Framework to Identify Detailed Routing Short Violations From a Placed Netlist.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Efficient computation of tridiagonal matrices largest eigenvalue.
J. Comput. Appl. Math., 2018

A machine learning framework to identify detailed routing short violations from a placed netlist.
Proceedings of the 55th Annual Design Automation Conference, 2018

Simultaneous Cost and QoS Optimization for Cloud Resource Allocation.
IEEE Trans. Netw. Serv. Manag., 2017

A Multiobjective Cooptimization of Buffer and Wire Sizes in High-Performance Clock Trees.
IEEE Trans. Circuits Syst. II Express Briefs, 2017

Detailed routing violation prediction during placement using machine learning.
Proceedings of the 2017 International Symposium on VLSI Design, Automation and Test, 2017

An efficient optimal clock network buffer sizing with slew consideration.
Proceedings of the 30th IEEE Canadian Conference on Electrical and Computer Engineering, 2017

A Parallel Method for the Computation of Matrix Exponential Based on Truncated Neumann Series.
Proceedings of the 24th IEEE Symposium on Computer Arithmetic, 2017

A fast force-directed simulated annealing for 3D IC partitioning.
Integr., 2016

Big Data Analytics for Modelling the Impact of Wind Power Generation on Competitive Electricity Market Prices.
Proceedings of the 49th Hawaii International Conference on System Sciences, 2016

A Detailed Routing-Aware Detailed Placement Technique.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

A Data-Driven Method to Detect the Abnormal Instances in an Electricity Market.
Proceedings of the 14th IEEE International Conference on Machine Learning and Applications, 2015

Minimizing Deployment Cost of Cloud-Based Web Application with Guaranteed QoS.
Proceedings of the 2015 IEEE Global Communications Conference, 2015

Sizing Digital Circuits Using Convex Optimization Techniques.
Proceedings of the Computational Intelligence in Digital and Network Designs and Applications, 2015

Variation-Aware Geometric Programming Models for the Clock Network Buffer Sizing Problem.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Optimal gate sizing using a self-tuning multi-objective framework.
Integr., 2014

GPU-Accelerated Solutions to Optimal Power Flow Problems.
Proceedings of the 47th Hawaii International Conference on System Sciences, 2014

A new a priori net length estimation technique for integrated circuits using radial basis functions.
Comput. Electr. Eng., 2013

Buffer sizing for clock networks using robust geometric programming considering variations in buffer sizes.
Proceedings of the International Symposium on Physical Design, 2013

A self-tuning multi-objective optimization framework for geometric programming with gate sizing applications.
Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013

A New Length-Based Algebraic Multigrid Clustering Algorithm.
VLSI Design, 2012

An algebraic multigrid-based algorithm for circuit clustering.
Appl. Math. Comput., 2012

Parallel clock tree synthesis.
Proceedings of the 25th IEEE Canadian Conference on Electrical and Computer Engineering, 2012

A pre-placement individual net length estimation model and an application for modern circuits.
Integr., 2011

Wirelength and congestion estimation for routability-driven placement.
Proceedings of the 2011 International Workshop on System Level Interconnect Prediction, 2011

A Multilevel Congestion-Based Global Router.
VLSI Design, 2009

A pre-placement net length estimation technique for mixed-size circuits.
Proceedings of the 11th International Workshop on System-Level Interconnect Prediction (SLIP 2009), 2009

Two Clustering Preprocessing Techniques for Large-Scale Circuits.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Clustering algorithms for circuit partitioning and placement problems.
Proceedings of the 18th European Conference on Circuit Theory and Design, 2007

A Structural Study and Hyperedge Clustering Technique for Large Scale Circuits.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2006