According to our database1, William Swartz authored at least 13 papers between 1990 and 2019.
Legend:Book In proceedings Article PhD thesis Other
Functional Obfuscation of Hardware Accelerators through Selective Partial Design Extraction onto an Embedded FPGA.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019
Design Obfuscation through Selective Post-Fabrication Transistor-Level Programming.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
Toward an Open-Source Digital Flow: First Learnings from the OpenROAD Project.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
A field programmable transistor array featuring single-cycle partial/full dynamic reconfiguration.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
A fast force-directed simulated annealing for 3D IC partitioning.
A Detailed Routing-Aware Detailed Placement Technique.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015
Analysis of post-placement length estimation.
Proceedings of the International Workshop on System Level Interconnect Prediction, 2012
Placement Using Simulated Annealing.
Proceedings of the Handbook of Algorithms for Physical Design Automation., 2008
Issues in global routing.
Proceedings of the 2008 International Symposium on Physical Design, 2008
Efficient timing closure without timing driven placement and routing.
Proceedings of the 41th Design Automation Conference, 2004
Timing Driven Placement for Large Standard Cell Circuits.
Proceedings of the 32st Conference on Design Automation, 1995
A new generalized row-based global router.
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993
New Algorithms for the Placement and Routing of Macro Cells.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990