Loganathan Lingappan

According to our database, Loganathan Lingappan authored at least 24 papers between 2003 and 2025.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2025

Improved Silent Data Error Detection Through Test Optimization Using Reinforcement Learning.

Manu Shamsa, John D. Martin, Mariano Phielipp, Thiago Macieira, Loganathan Lingappan, Brad Kelly, David Lerner, Michael Tucknott, Ethan Hansen

Proceedings of the IEEE International Reliability Physics Symposium, 2025

2018

Online Scan Diagnosis : A Novel Approach to Volume Diagnosis.

I-De Huang, Pallav Gupta, Loganathan Lingappan, Vijay Gangaram

Proceedings of the IEEE International Test Conference, 2018

An online framework for diagnosis of multiple defects in scan chains.

Sarmad Tanwir, Michael S. Hsiao, Loganathan Lingappan

Proceedings of the 19th International Symposium on Quality Electronic Design, 2018

2017

A Test Pattern Quality Metric for Diagnosis of Multiple Stuck-at and Transition faults.

Sarmad Tanwir, Michael S. Hsiao, Loganathan Lingappan

Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

2016

Hardware-in-the-loop model-less diagnostic test generation.

Sarmad Tanwir, Michael S. Hsiao, Loganathan Lingappan

Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2016

2015

Information-theoretic and statistical methods of failure log selection for improved diagnosis.

Sarmad Tanwir, Sarvesh Prabhu, Michael S. Hsiao, Loganathan Lingappan

Proceedings of the 2015 IEEE International Test Conference, 2015

2013

Test generation for circuits with embedded memories using SMT.

Sarvesh Prabhu, Michael S. Hsiao, Loganathan Lingappan, Vijay Gangaram

Proceedings of the 18th IEEE European Test Symposium, 2013

2012

A SMT-based diagnostic test generation method for combinational circuits.

Sarvesh Prabhu, Michael S. Hsiao, Loganathan Lingappan, Vijay Gangaram

Proceedings of the 30th IEEE VLSI Test Symposium, 2012

A Novel SMT-Based Technique for LFSR Reseeding.

Sarvesh Prabhu, Michael S. Hsiao, Loganathan Lingappan, Vijay Gangaram

Proceedings of the 25th International Conference on VLSI Design, 2012

2011

Strategies for scalable symbolic execution-driven test generation for programs.

Saparya Krishnamoorthy, Michael S. Hsiao, Loganathan Lingappan

Sci. China Inf. Sci., 2011

An Efficient 2-Phase Strategy to Achieve High Branch Coverage.

Sarvesh Prabhu, Michael S. Hsiao, Saparya Krishnamoorthy, Loganathan Lingappan, Vijay Gangaram, Jim Grundy

Proceedings of the 20th IEEE Asian Test Symposium, 2011

2010

Tackling the Path Explosion Problem in Symbolic Execution-Driven Test Generation for Programs.

Saparya Krishnamoorthy, Michael S. Hsiao, Loganathan Lingappan

Proceedings of the 19th IEEE Asian Test Symposium, 2010

2009

Fast Enhancement of Validation Test Sets for Improving the Stuck-at Fault Coverage of RTL Circuits.

Loganathan Lingappan, Vijay Gangaram, Niraj K. Jha, Sreejit Chakravarty

IEEE Trans. Very Large Scale Integr. Syst., 2009

2007

Satisfiability-Based Automatic Test Program Generation and Design for Testability for Microprocessors.

Loganathan Lingappan, Niraj K. Jha

IEEE Trans. Very Large Scale Integr. Syst., 2007

A Test Generation Framework for Quantum Cellular Automata Circuits.

Pallav Gupta, Niraj K. Jha, Loganathan Lingappan

IEEE Trans. Very Large Scale Integr. Syst., 2007

Efficient Design for Testability Solution Based on Unsatisfiability for Register-Transfer Level Circuits.

Loganathan Lingappan, Niraj K. Jha

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Fast Enhancement of Validation Test Sets to Improve Stuck-at Fault Coverage for RTL circuits.

Loganathan Lingappan, Vijay Gangaram, Niraj K. Jha

Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

2006

Test-Volume Reduction in Systems-on-a-Chip Using Heterogeneous and Multilevel Compression Techniques.

Loganathan Lingappan, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha, Srimat T. Chakradhar

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Satisfiability-based test generation for nonseparable RTL controller-datapath circuits.

Loganathan Lingappan, Srivaths Ravi, Niraj K. Jha

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Improving the Performance of Automatic Sequential Test Generation by Targeting Hard-to-Test Faults.

Loganathan Lingappan, Niraj K. Jha

Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

Test generation for combinational quantum cellular automata (QCA) circuits.

Pallav Gupta, Niraj K. Jha, Loganathan Lingappan

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005

Unsatisfiability Based Efficient Design for Testability Solution for Register-Transfer Level Circuits.

Loganathan Lingappan, Niraj K. Jha

Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

Heterogeneous and Multi-Level Compression Techniques for Test Volume Reduction in Systems-on-Chip.

Loganathan Lingappan, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha, Srimat T. Chakradhar

Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

2003

Test Generation for Non-separable RTL Controller-datapath Circuits using a Satisfiability based Approach.

Loganathan Lingappan, Srivaths Ravi, Niraj K. Jha

Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003