Luca Di Nunzio

Orcid: 0000-0002-4312-7939

According to our database1, Luca Di Nunzio authored at least 49 papers between 2008 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Design Space Exploration for Edge Machine Learning Featured by MathWorks FPGA DL Processor: A Survey.
IEEE Access, 2024

2023
Efficient Digital Implementation of a Multirate-Based Variable Fractional Delay Filter for Wideband Beamforming.
IEEE Trans. Circuits Syst. II Express Briefs, June, 2023

An RNS-Based Initial Absolute Position Estimator for Electrical Encoders.
IEEE Access, 2023

A RISC-V Hardware Accelerator for Q-Learning Algorithm.
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2023

2022
Design Space Exploration Based Methodology for Residue Number System Digital Filters Implementation.
IEEE Trans. Emerg. Top. Comput., 2022

Sensing and Detection of Traffic Signs Using CNNs: An Assessment on Their Performance.
Sensors, 2022

An FPGA-based multi-agent Reinforcement Learning timing synchronizer.
Comput. Electr. Eng., 2022

FPGA-Based Road Crack Detection Using Deep Learning.
Proceedings of the Advances in System-Integrated Intelligence, 2022

Automatic IP Core Generator for FPGA-Based Q-Learning Hardware Accelerators.
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2022

2021
M-PSK Demodulator With Joint Carrier and Timing Recovery.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

A Parallel Hardware Implementation for 2-D Hierarchical Clustering Based on Fuzzy Logic.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

Design and FPGA Implementation of a Low Power OFDM Transmitter for Narrow-Band IoT.
Proceedings of the Scholar's Yearly Symposium of Technology, 2021

A M-PSK Timing Recovery Loop Based on Q-Learning.
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2021

"MR Q-Learning" Algorithm for Efficient Hardware Implementations.
Proceedings of the 55th Asilomar Conference on Signals, Systems, and Computers, 2021

2020
AW-SOM, an Algorithm for High-Speed Learning in Hardware Self-Organizing Maps.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

N-Dimensional Approximation of Euclidean Distance.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

An Action-Selection Policy Generator for Reinforcement Learning Hardware Accelerators.
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2020

FPGA Implementation of Q-RTS for Real-Time Swarm Intelligence Systems.
Proceedings of the 54th Asilomar Conference on Signals, Systems, and Computers, 2020

2019
An Efficient Hardware Implementation of Reinforcement Learning: The Q-Learning Algorithm.
IEEE Access, 2019

A Reinforcement Learning-Based QAM/PSK Symbol Synchronizer.
IEEE Access, 2019

Digital Signal Processing Accelerator for RISC-V.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

Acoustic Emissions Detection and Ranging of Cracks in Metal Tanks Using Deep Learning.
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2019

Approximated Canonical Signed Digit for Error Resilient Intelligent Computation.
Proceedings of the 53rd Asilomar Conference on Signals, Systems, and Computers, 2019

2018
Channel estimation for high speed unmanned aerial vehicle with STBC in MIMO radio links.
Int. J. Comput. Vis. Robotics, 2018

Digital Architecture and ASIC Implementation of Wideband Delta DOR Spacecraft Onboard Tracker.
Proceedings of the 15th International Conference on Synthesis, 2018

Setup and experimental results analysis of COTS Camera and SRAMs at the ISIS neutron facility.
Proceedings of the 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2018

Efficient Ensemble Machine Learning Implementation on FPGA Using Partial Reconfiguration.
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2018

A Power Efficient Digital Front-End for Cognitive Radio Systems.
Proceedings of the 52nd Asilomar Conference on Signals, Systems, and Computers, 2018

2017
Hardware design of LIF with Latency neuron model with memristive STDP synapses.
Integr., 2017

Robust throughput boosting for low latency dynamic partial reconfiguration.
Proceedings of the 30th IEEE International System-on-Chip Conference, 2017

A new electric encoder position estimator based on the Chinese Remainder Theorem for the CMG performance improvements.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

FPGA Implementation of a Low-Power QRS Extractor.
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2017

A Wireless Sensor Node for Acoustic Emission Non-destructive Testing.
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2017

2016
Design and characterization of a high-safety hardware/software module for the acquisition of Eurobalise telegrams.
Proceedings of the 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2016

ZnO-rGO Composite Thin Film Resistive Switching Device: Emulating Biological Synapse Behavior.
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2016

Compressive Sensing Reconstruction for Complex System: A Hardware/Software Approach.
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2016

Dynamically-loaded Hardware Libraries (HLL) technology for audio applications.
Proceedings of the 50th Asilomar Conference on Signals, Systems and Computers, 2016

2015
A Wireless Sensor Node Based on Microbial Fuel Cell.
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2015

2014
TDES cryptography algorithm acceleration using a reconfigurable functional unit.
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

2013
A Reconfigurable Functional Unit for Modular Operations.
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2013

Spiking neural networks based on LIF with latency: Simulation and synchronization effects.
Proceedings of the 2013 Asilomar Conference on Signals, 2013

2012
Integration of butterfly and inverse butterfly nets in embedded processors: Effects on power saving.
Proceedings of the Conference Record of the Forty Sixth Asilomar Conference on Signals, 2012

2011
Fine-grain Reconfigurable Functional Unit for embedded processors.
Proceedings of the Conference Record of the Forty Fifth Asilomar Conference on Signals, 2011

2010
Algorithm acceleration on LEON-2 processor using a reconfigurable bit manipulation unit.
Proceedings of the 8th Workshop on Intelligent Solutions in Embedded Systems, 2010

VLSI implementation of reconfigurable cells for RFU in embedded processors.
Proceedings of the 17th IEEE International Conference on Electronics, 2010

2009
Speed-up of RISC Processor Computation using ADAPTO.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Arithmetic/Logic Blocks for Fine-grained Reconfigurable Units.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2008
ADAPTO: full-adder based reconfigurable architecture for bit level operations.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

A full-adder based reconfigurable architecture for fine grain applications: ADAPTO.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008


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