Mahdieh Grailoo

Orcid: 0000-0003-1823-4211

According to our database1, Mahdieh Grailoo authored at least 8 papers between 2010 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
Deep Quantization of Graph Neural Networks with Run-Time Hardware-Aware Training.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2024

2022
Preventing Distillation-based Attacks on Neural Network IP.
CoRR, 2022

Hardware Trojans for Confidence Reduction and Misclassifications on Neural Networks.
Proceedings of the 23rd International Symposium on Quality Electronic Design, 2022

2017
Improved Range Analysis in Fixed-Point Polynomial Data-Path.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

2016
Energy and Area Efficient Three-Input XOR/XNORs With Systematic Cell Design Methodology.
IEEE Trans. Very Large Scale Integr. Syst., 2016

UAFEA: Unified Analytical Framework for IA/AA-Based Error Analysis of Fixed-Point Polynomial Specifications.
IEEE Trans. Circuits Syst. II Express Briefs, 2016

Power and Energy Efficient Standard Cells with CDM Logic Style for Optimization of Multiplier Structures.
Proceedings of the 7th International Conference on Computing Communication and Networking Technologies, 2016

2010
Cell Design Methodology Based on Transmission Gate for Low-Power High-Speed Balanced XOR-XNOR Circuits in Hybrid-CMOS Logic Style.
J. Low Power Electron., 2010


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